CY7C1308DV25C-167BZC Cypress Semiconductor Corp, CY7C1308DV25C-167BZC Datasheet - Page 5

• Manufacturer Part Number: CY7C1308DV25C-167BZC
• Description: IC SRAM 9MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1308DV25C-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR
• Memory Size: 9M (256K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Truth Table
Linear Burst Address Table
Document #: 001-04310 Rev. *A
Write Cycle:
Load address; wait one cycle; input
write data on 2 consecutive K and
K rising edges.
Read Cycle:
Load address; wait one cycle; read
data on 2 consecutive C and C
rising edges.
NOP: No Operation
Standby: Clock Stopped
Notes
1. The above application shows 2 DDR I being used.
2. X = “Don't Care“, H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected and the outputs are in a tristate condition.
4. “A1” represents address location latched by the devices when transaction was initiated. A2, A3, and A4 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 and t+2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. This signal was HIGH on previous K clock rise. Initiating consecutive Write operations on consecutive K clock rises is not permitted. The device ignores the second
9. This signal was LOW on previous K clock rise. Initiating consecutive Read operations on consecutive K clock rises is not permitted.The device ignores the second
symmetrically.
Write request.
Read request.
First Address (External)
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
MASTER
ASIC)
(CPU
BUS
or
Operation
X..X00
X..X01
X..X10
X..X11
[2, 3, 4, 5, 6, 7]
Return CLK#
Source CLK#
Cycle Start#
Return CLK
Source CLK
Addresses
R/W#
DQ
R = 50ohms
Stopped
Second Address (Internal)
Vterm = 0.75V
Vterm = 0.75V
DQ
L-H
L-H
L-H
A
K
↑
LD#
represents rising edge.
Figure 1. Application Example
SRAM#1
R/W#
X..X01
X..X10
X..X00
X..X11
PRELIMINARY
LD
H
L
L
X
C C#
CQ/CQ#
K
ZQ
R/W
K#
H
L
X
X
[8]
[9]
D(A1)at
K(t+1)↑
Q(A1) at
C(t+1)↑
High-Z
Previous State Previous State Previous State Previous State
R = 250ohms
Third Address (Internal)
DQ
[1]
X..X10
X..X00
X..X01
X..X11
D(A2) at
K(t+1)↑
Q(A2) at
C(t+1) ↑
High-Z
DQ
A
DQ
LD#
SRAM#2
R/W#
D(A3) at
K(t+2) ↑
Q(A3) at
C(t+2)↑
High-Z)
C C#
CY7C1308DV25C
Fourth Address (Internal)
CQ/CQ#
DQ
K
ZQ
K#
X..X00
X..X01
X..X10
X..X11
D(A4) at
K(t+2) ↑
Q(A4) at
C(t+2) ↑
High-Z
R = 250ohms
Page 5 of 18
DQ
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