CY7C1308DV25C-167BZC Cypress Semiconductor Corp, CY7C1308DV25C-167BZC Datasheet - Page 3

• Manufacturer Part Number: CY7C1308DV25C-167BZC
• Description: IC SRAM 9MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1308DV25C-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR
• Memory Size: 9M (256K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Introduction
Functional Overview
The CY7C1308DV25C is a synchronous pipelined Burst SRAM
equipped with DDR interface.
Accesses are initiated on the positive input clock (K). All
synchronous input timing is referenced from the rising edge of
the input clocks (K and K) and all output timing is referenced to
the rising edge of output clocks (C and C or K and K when in
single clock mode).
All synchronous data inputs (D
controlled by the input clocks (K and K). All synchronous data
outputs (Q
rising edge of the output clocks (C and C or K and K when in
single clock mode).
Document #: 001-04310 Rev. *A
C
K
K
CQ
CQ
ZQ
TDO
TCK
TDI
TMS
NC
NC/18M
NC/36M
GND/72M
GND/144M
V
V
V
V
REF
DD
SS
DDQ
Name
[35:0]
) pass through output registers controlled by the
Power Supply
Power Supply
(continued)
Input Clock
Input Clock
Input Clock
Echo Clock
Echo Clock
Reference
Ground
Output
Input-
Input
Input
Input
Input
Input
Input
N/A
N/A
N/A
I/O
[35:0]
) pass through input registers
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
are initiated on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q
CQ is Referenced with Respect to C. This is a free running clock and is synchronized
to the output clock (C) of the DDR I. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ is Referenced with Respect to C. This is a free running clock and is synchronized
to the output clock (C) of the DDR I. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ and Q
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
be connected directly to GND or left unconnected.
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Address Expansion for 18M. This is not connected to the die.
Address Expansion for 36M. This is not connected to the die.
Address Expansion for 72M. This should be tied LOW.
Address Expansion for 144M. This should be tied LOW.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and outputs as well as AC measurement points.
Power supply inputs to the core of the device.
Ground for the device.
Power supply inputs for the outputs of the device.
PRELIMINARY
DD
, which enables the minimum impedance mode. This pin cannot
All synchronous control (R/W, LD) inputs pass through input
registers controlled by the rising edge of the input clocks (K and
K).
Read Operations
The CY7C1308DV25C is organized internally as an array of
256K x 36. Accesses are completed in a burst of four sequential
36-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register and the least two significant bits of
the address are presented to the burst counter. The burst
counter increments the address in a linear fashion. Following the
next K clock rise the corresponding 36-bit word of data from this
address location is driven onto the Q
timing reference. On the subsequent rising edge of C the next
36-bit data word from the address location generated by the
burst counter is driven onto the Q
Description
[35:0]
[35:0]
[35:0]
when in single clock mode. All accesses
Figure 1
output impedance are set to 0.2 x RQ,
when in single clock mode.
on page 5 for further details.
[35:0]
CY7C1308DV25C
[35:0]
. This process continues
using C as the output
Page 3 of 18
[+] Feedback