VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet - Page 33

• Manufacturer Part Number: VRS51C1100-40-Q-ISPV2
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q-ISPV2

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

Modifying the Order of Priority
The VRS51C1100 allows the user to modify the natural
priority of the interrupts. The order can be modified by
programming the bits in the IP (Interrupt Priority)
register. When any bit in this register is set to 1, it
gives the corresponding source priority over interrupts
coming
corresponding IP bits set to 1.
The IP register is represented in the table below.
T
The Watchdog Timer
The VRS51C1100 watchdog timer (WDT) is a 16-bit
free-running counter operating from an independent
250KHz internal RC oscillator. The overflow of the
watchdog timer counter will reset the processor. The
WDT is a useful safety measure for systems that are
susceptible to noise, power glitches and other
conditions that can cause the software to go into
infinite dead loops or runaways; The WDT provides a
recovery
conditions.
Watchdog Timer Registers
The configuration and use of the VRS51C1100
watchdog timer is handled by three registers:
WDTKEY, WDTCTRL and SYSCON.
The WDTKEY register ensures that the watchdog timer
is not inadvertently reset in case of program
malfunction.
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ABLE
5
4
3
2
1
0
Bit
7
6
VRS51C1100
EA
7
34: IP I
PT2
PS
PT1
PX1
PT0
PX0
Mnemonic
-
-
NTERRUPT
6
-
from
mechanism
P
ET2
RIORITY
5
sources
Description
Gives Timer 2 Interrupt Higher Priority
Gives Serial Port Interrupt Higher Priority
Gives Timer 1 Interrupt Higher Priority
Gives INT1 Interrupt Higher Priority
Gives Timer 0 Interrupt Higher Priority
Gives INT0 Interrupt Higher Priority
R
EGISTER
ES
4
from
–SFR B8
that
ET1
3
H
abnormal
don’t
EX1
2
have
ET0
1
software
EX0
their
0
T
The WDTCTRL register is, by default, configured as a
read-only register. To modify its contents, two
consecutive write operations to the WDTKEY register
must be performed:
MOV
MOV
Once the configuration or WDT reset operation is
complete, the WDTCTRL register can be restored to
read-only by writing the following sequence into the
WDTKEY register:
MOV
MOV
Once the WDT operation is activated, the user
software must clear it periodically. If the WDT is not
cleared, its overflow will trigger a reset of the
VRS51C1100.
T
The WDT timeout delay can be adjusted by configuring
the clock divider input on the WDT’s time base source
clock.
[WDTPS2~WDTPS0] bits of the WDT control register
should be set accordingly.
The following table provides the approximate timeout
periods associated with different values of the
WDTPSx bits of the watchdog timer register.
ABLE
ABLE
Bit
7:0
Bit
7
6
5
[4:3]
2
1
0
WDTE
7
7
35: W
36: W
ATCH
WDTKEY,#01Eh
WDTKEY,#0E1h
WDTKEY,#0E1h
WDTKEY,#01Eh
ATCH
To
Mnemonic
WDTKEY
Unused
Mnemonic
WDTE
Unused
WDTCLR
Unused
WDTPS2
WDTPS1
WDTPS0
D
D
OG
OG
6
6
T
T
IMER
IMER
select
K
C
EY REGISTER
ONTROL
WDT
CLR
5
5
Description
Watch Dog Key
Description
Watchdog Timer Enable Bit
0: Watchdog Timer is disabled
1: Watchdog Timer is enabled
-
Watchdog Timer Counter Clear Bit
-
Clock Source Divider Bit 2
Clock Source Divider Bit 1
Clock Source Divider Bit 0
WDTKEY7:0
(WDTCTRL) – SFR 9F
the
Unused
4
4
: WDTKEY – SFR 97
3
3
divider
WDT
PS2
2
2
H
page 33 of 50
H
value,
WDT
PS1
1
1
WDT
PS0
0
0
the