VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet - Page 34

• Manufacturer Part Number: VRS51C1100-40-Q-ISPV2
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q-ISPV2

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

T
To enable the WDT, the user must set bit 7 (WDTE) of
the WDTCTRL register to 1. The 16-bit counter will
start to count using the internal 250kHz oscillator as a
clock source, divided according to the value of the
WDTPS2~WDTPS0 bits.
To clear the WDT, set the WDTCLR bit of the
WDTCTRL to 1. This action will clear the contents of
the 16-bit counter and force it to restart.
If the watchdog timer overflows, it will reset the
processor, the WDR bit (7) of SYSCON register will be
set to 1 and the WDTE bit will be cleared to 0. The
user should check the WDR bit if an unexpected reset
has taken place. If the WDR bit is set, the processor
reset
______________________________________________________________________________________________
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ABLE
VRS51C1100
37: WDT T
was
IMEOUT
WDTPS [2:0]
caused
P
ERIOD AT
000
001
010
011
100
101
110
111
by
the
WDT Period
131.07ms
262.14ms
16.38ms
32.77ms
65.54ms
2.05ms
4.10ms
8.19ms
watchdog
timer.
WDT Initialization Example
The following program example demonstrates the
watchdog timer initialization sequence and the routine
to periodically clear it.
;*** VARIABLE DEFINITION ***
CPTR
PORTVAL
;*** PROGRAM START HERE ****
ORG
;*** MAIN PROGRAM START ***
ORG
;*** CHECK IF RESET WAS CAUSED BY THE WATCHDOG TIMER
START:
INITWDT:
WDTRESET: NOP
;*** SEQUENCE TO CLEAR THE WATCHDOG TIMER (SAME AS CONFIG)
LOOP:
0000h
0100h
EQU
EQU
LJMP
MOV
ANL
JNZ
MOV
MOV
MOV WDTCTRL,#10000010B ;CONFIG THE WATCHDOG TIMER
MOV
MOV
MOV
MOV
CPL
MOV
MOV
;MOV
;MOV
;MOV
;MOV
;MOV
(…)
LJMP
WDTRESET
A,#80H
A
A,SYSCON
WDTKEY,#01EH ;UNLOCK THE WDTCTRL REG ACCESS IN
WDTKEY,#0E1H ;WRITING MODE
WDTKEY,#0E1H ;LOCK THE WDTCTRL ACCESS IN WRITING
WDTKEY,#01EH
PORTVAL,#00H
A,PORTVAL
PORTVAL,A
P1,A
START
WDTKEY,#01EH ;UNLOCK THE WDTCTRL REG ACCESS IN
WDTKEY,#0E1H
WDTCTRL,#10100010B
WDTKEY,#0E1H ;LOCK THE WDTCTRL ACCESS IN WRITING
WDTKEY,#01EH
LOOP
020H
00H
;WDT BIT SET -> WE GOT A WDT RESET
;BIT 7 - WDTEN=1 WATCHDOG TIMER ENABLE
;BIT 6 - UNUSED
;BIT 5 - WDTCLR=1 WATCHDOG CLEAR
;BIT 4:3 - UNUSED
;BIT 2:0 - WDTCLK=010 - WDT TIMEOUT = 8mS
;INIT PORT VALUE TO 00H
;IF THE WDT CAUSE THE RESET INIT PORTVAL
;TOGGLE P1 VALUE
;WRITING MODE
;BIT 7 - WDTEN=1 WDT ENABLE
;BIT 6 - UNUSED
;BIT 5 - WDTCLR=1 WDT CLEAR
;BIT 4:3 - UNUSED
;BIT 2:0 - WDTCLK=010 - WDT TIMEOUT = 8mS
;CONFIG THE WDT TIMER
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