VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet - Page 36

• Manufacturer Part Number: VRS51C1100-40-Q-ISPV2
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q-ISPV2

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

PWM Data Registers
The following tables describe the PWM data registers.
The PWMDx bits hold the content of the PWM data
register and determine the duty cycle of the PWM
output waveforms. The NPx[2:0] bits will insert narrow
pulses into the 8-PWM-cycle frame.
T
T
T
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ABLE
ABLE
ABLE
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
VRS51C1100
PWMD0.4
PWMD0.0
PWMD1.4
PWMD1.0
PWMD2.4
PWMD2.0
40: PWM D
41: PWM D
42: PWM D
Mnemonic
PWMD0.4
PWMD0.3
PWMD0.2
PWMD0.1
PWMD0.0
NP0.2
NP0.1
NP0.0
Mnemonic
PWMD1.4
PWMD1.3
PWMD1.2
PWMD1.1
PWMD1.0
NP1.2
NP1.1
NP1.0
7
3
7
3
7
3
ATA
ATA
ATA
R
R
R
EGISTER
EGISTER
EGISTER
PWMD0.3
PWMD1.3
PWMD2.3
NP0.2
NP1.2
NP2.2
6
2
Description
Contents of PWM Data Register 0 Bit 4
Contents of PWM Data Register 0 Bit 3
Contents of PWM Data Register 0 Bit 2
Contents of PWM Data Register 0 Bit 1
Contents of PWM Data Register 0 Bit 0
Inserts Narrow Pulses in a 8-PWM-Cycle
Frame
6
2
Description
Contents of PWM Data Register 1 Bit 4
Contents of PWM Data Register 1 Bit 3
Contents of PWM Data Register 1 Bit 2
Contents of PWM Data Register 1 Bit 1
Contents of PWM Data Register 1 Bit 0
Inserts Narrow Pulses in a 8-PWM-Cycle
Frame
6
2
0 (PWMD0) – SFR A4
1 (PWMD1) – SFR A5
2 (PWMD2) – SFR A6
PWMD0.2
PWMD1.2
PWMD2.2
NP0.1
NP1.1
NP2.1
5
1
5
1
5
1
H
H
H
PWMD0.1
PWMD1.1
PWMD2.1
NP0.0
NP1.0
NP2.0
4
0
4
0
4
0
T
The table below shows the number of PWM cycles
inserted into an 8-cycle frame when we vary the NP
number.
ABLE
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
NP[2:0]
PWMD3.4
PWMD3.0
43: PWM D
Mnemonic
PWMD2.4
PWMD2.3
PWMD2.2
PWMD2.1
PWMD2.0
NP2.2
NP2.1
NP2.0
Mnemonic
PWMD3.4
PWMD3.3
PWMD3.2
PWMD3.1
PWMD3.0
NP3.2
NP3.1
7
3
000
001
010
011
100
101
110
111
ATA
R
EGISTER
PWMD3.3
NP3.2
Description
Contents of PWM Data Register 2 Bit 4
Contents of PWM Data Register 2 Bit 3
Contents of PWM Data Register 2 Bit 2
Contents of PWM Data Register 2 Bit 1
Contents of PWM Data Register 2 Bit 0
Inserts Narrow Pulses in a 8-PWM-Cycle
Frame
Description
Contents of PWM Data Register 3 Bit 4
Contents of PWM Data Register 3 Bit 3
Contents of PWM Data Register 3 Bit 2
Contents of PWM Data Register 3 Bit 1
Contents of PWM Data Register 3 Bit 0
Inserts Narrow Pulses in a 8-PWM-Cycle
Frame
6
2
3 (PWMD3) – SFR A7
Number of PWM cycles inserted
in an 8-cycle frame
PWMD3.2
NP3.1
5
1
H
0
1
2
3
4
5
6
7
page 36 of 50
PWMD3.1
NP3.0
4
0