VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet - Page 8

• Manufacturer Part Number: VRS51C1100-40-Q-ISPV2
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q-ISPV2

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

VRS51C1100 IAP feature
The VRS51C1100 IAP feature allows the processor to
self-program its program and data Flash memory from
within the user program.
Five SFR registers serve to control the IAP operation.
The description of these registers is provided below.
System Control Register
The system control register controls the activation of
the data Flash and the expanded RAM and serves to
monitor the watchdog timer status.
T
The WDR bit of the SYSCON register indicates
whether the system has been reset due to the overflow
of the watchdog timer. For this reason, users should
check the WDR bit whenever an unexpected reset
occurs.
Setting the DFLASHE bit of the SYSCON register to 1
activates the 64KB on-chip data Flash memory, which
is disabled by default.
The IAPE bit is used to activate the IAP function.
When set to 1, the XRAME bit enables the expanded
768 bytes of RAM. Bit 0 of this register is the ALE
output inhibit bit. Setting this bit to 1 will inhibit the
Fosc/6Hz clock signal output to the ALE pin.
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ABLE
Bit
7
6
5
4
3
2
1
0
WDR
VRS51C1100
7
6: S
YSTEM
Mnemonic
WDR
Unused
Unused
Unused
DFLASHE
IAPE
XRAME
ALEI
6
Unused
C
ONTROL
5
R
EGISTER
4
Description
This is the watchdog timer reset bit. It will
be set to 1 when the reset signal generated
by WDT overflows.
-
-
-
Data Flash memory Enable
0: Data Flash is Disabled
1: Data Flash is Enabled
IAP function enable bit
0: IAP is Disabled
1: ISP is Enabled
768 byte on-chip enable bit
ALE output inhibit bit, which is used to
reduce EMI.
0: ALE active
1: ALE activity is inhibited
DFLASHE
(SYSCON) – SFR BF
3
IAPE
2
H
XRAME
1
ALEI
0
IAP Flash Address and Data Registers
The IAPFADHI and IAPADLO registers are used to
specify at which address the IAP function will be
performed.
T
T
The IAPFDATA SFR register contains the data byte
required to perform the IAP function.
T
ABLE
ABLE
ABLE
7
7
7
7:IAP F
8:IAP F
9:IAP F
LASH
6
LASH
6
LASH
6
A
A
D
DDRESS
DDRESS
ATA
5
5
5
R
EGISTER
H
L
OW
IGH
IAPFADLO[15:8]
IAPFADHI[15:8]
IAPFDATA[7:0]
4
(IAPFADLO) - SFR F5
4
4
(IAPFADHI) - SFR F4
(IAPFDATA) - SFR F6
3
3
3
2
2
2
H
H
H
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