EVAL-ADXL350Z-S Analog Devices, EVAL-ADXL350Z-S Datasheet - Page 17
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EVAL-ADXL350Z-S
Manufacturer Part Number
EVAL-ADXL350Z-S
Description
Daughter Cards & OEM Boards EB
Manufacturer
Analog Devices
Series
ADXL350r
Datasheet
1.EVAL-ADXL350Z-S.pdf
(36 pages)
Specifications of EVAL-ADXL350Z-S
Rohs
yes
Product
Satellite Boards
Description/function
3 axis accelerometer evaluation board
Interface Type
I2C, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2 V to 3.6 V
Factory Pack Quantity
1
For Use With
ADXL350
Data Sheet
Table 9. SPI Digital Input/Output Voltage
Parameter
Digital Input
Low Level Input Voltage (V
High Level Input Voltage (V
Low Level Input Current (I
High Level Input Current (I
Digital Output
Low Level Output Voltage (V
High Level Output Voltage (V
Low Level Output Current (I
High Level Output Current (I
Pin Capacitance
1
Table 10. SPI Timing (T
Parameter
f
t
t
t
t
t
t
t
t
t
t
1
2
3
SCLK
SCLK
DELAY
QUIET
DIS
CS,DIS
S
M
SDO
SETUP
HOLD
Limits based on characterization results, not production tested.
The CS , SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
Limits are based on characterization results, characterized with f
The timing values are measured corresponding to the input thresholds (V
Min
200
10
10
250
0.4 × t
0.4 × t
10
10
A
IL
SCLK
SCLK
IH
IL
)
= 25°C, V
IH
)
)
OL
OH
OL
Limit
)
OH
)
)
)
)
2, 3
Max
5
100
95
S
= 2.5 V, V
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD I/O
= 1.8 V)
SCLK
Test Conditions
V
V
I
I
V
V
f
OL
OH
IN
IN
IN
OL
OH
= 1 MHz, V
= 5 MHz and bus load capacitance of 100 pF; not production tested.
= 10 mA
= V
= 0 V
= −4 mA
= V
= V
Description
CS falling edge to SCLK falling edge
SCLK rising edge to CS rising edge
CS rising edge to SDO disabled
CS deassertion between SPI communications
SPI clock frequency
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
SCLK low pulse width (space)
SCLK high pulse width (mark)
SCLK falling edge to SDO transition
SDI valid before SCLK rising edge
SDI valid after SCLK rising edge
Rev. 0 | Page 17 of 36
DD I/O
OL, max
OH, min
IL
1
and V
IN
IH
) given in Table 9.
= 2.5 V
Min
0.7 × V
−0.1
0.8 × V
10
DD I/O
DD I/O
Limit
Max
0.3 × V
0.1
0.2 × V
−4
8
1
DD I/O
DD I/O
ADXL350
Unit
V
V
µA
µA
V
V
mA
mA
pF