EVAL-ADXL350Z-S Analog Devices, EVAL-ADXL350Z-S Datasheet - Page 28

• Manufacturer Part Number: EVAL-ADXL350Z-S
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL350r

Specifications of EVAL-ADXL350Z-S

• Rohs: yes
• Product: Satellite Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL350

ADXL350
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
A 1 μF tantalum capacitor (C
(C
for testing and is recommended to adequately decouple the
accelerometer from noise on the power supply. If additional
decoupling is necessary, a resistor or ferrite bead, no larger than
100 Ω, in series with V
the bypass capacitance on V
parallel with a 0.1 μF ceramic capacitor may also improve noise.
Care should be taken to ensure that the connection from the
ADXL350
because noise transmitted through ground has an effect similar
to noise transmitted through V
V
on the V
the supplies as previously mentioned may be necessary.
MECHANICAL CONSIDERATIONS FOR MOUNTING
The
close to a hard mounting point of the PCB to the case. Mounting
the
Figure 59, may result in large, apparent measurement errors due
to undampened PCB vibration. Locating the accelerometer near
a hard mounting point ensures that any PCB vibration at the
accelerometer is above the accelerometer’s mechanical sensor
resonant frequency and, therefore, effectively invisible to the
accelerometer.
TAP DETECTION
The tap interrupt function is capable of detecting either single
or double taps. The following parameters are shown in Figure 60
for a valid single and valid double tap event:
•
INTERRUPT
DD I/O
IO
CONTROL
ADXL350
) at V
ADXL350
The tap detection threshold is defined by the THRESH_TAP
register (Address 0x1D).
be separate supplies to minimize digital clocking noise
S
DD I/O
supply. If this is not possible, additional filtering of
ground to the power supply ground has low impedance
Figure 59. Incorrectly Placed Accelerometers
at an unsupported PCB location, as shown in
placed close to the
should be mounted on the PCB in a location
C
MOUNTING POINTS
S
Figure 58. Application Diagram
ACCELEROMETERS
INT1
INT2
V
S
V
S
S
may be helpful. Additionally, increasing
SDO/ALT ADDRESS
ADXL350
PCB
GND
S
S
) at V
SDA/SDI/SDIO
to a 10 μF tantalum capacitor in
S
SCL/SCLK
. It is recommended that V
V
V
DD I/O
DD I/O
S
ADXL350
and a 0.1 μF ceramic capacitor
CS
C
IO
supply pins is used
3- OR 4-WIRE
SPI OR I
INTERFACE
2
C
S
and
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•
•
•
If only the single tap function is in use, the single tap interrupt
is triggered when the acceleration goes below the threshold, as
long as DUR has not been exceeded. If both single and double
tap functions are in use, the single tap interrupt is triggered when
the double tap event has been either validated or invalidated.
Several events can occur to invalidate the second tap of a double
tap event. First, if the suppress bit in the TAP_AXES register
(Address 0x2A) is set, any acceleration spike above the threshold
during the latency time (set by the latent register) invalidates
the double tap detection, as shown in Figure 61.
Figure 60. Tap Interrupt Function with Valid Single and Double Taps
TIME LIMIT
FOR TAPS
The maximum tap duration time is defined by the DUR
register (Address 0x21).
The tap latency time is defined by the latent register
(Address 0x22) and is the waiting period from the end of
the first tap until the start of the time window, when a
second tap can be detected, which is determined by the
value in the window register (Address 0x23).
The interval after the latency time (set by the latent register) is
defined by the window register. Although a second tap must
begin after the latency time has expired, it need not finish
before the end of the time defined by the window register.
(DUR)
Figure 61. Double Tap Event Invalid Due to High g Event
LATENCY
(LATENT)
TIME
FIRST TAP
TIME LIMIT FOR
SINGLE TAP
INTERRUPT
TAPS (DUR)
TIME (LATENT)
LATENCY
SECOND TAP (WINDOW)
When the Suppress Bit Is Set
TIME WINDOW FOR
SECOND TAP
INVALIDATES DOUBLE TAP IF
DOUBLE TAP
TIME WINDOW FOR SECOND
INTERRUPT
SUPRESS BIT SET
TAP (WINDOW)
Data Sheet
THRESHOLD
(THRESH_TAP)