EVAL-ADXL350Z-S Analog Devices, EVAL-ADXL350Z-S Datasheet - Page 22

• Manufacturer Part Number: EVAL-ADXL350Z-S
• Description: Daughter Cards & OEM Boards EB
• Manufacturer: Analog Devices
• Series: ADXL350r

Specifications of EVAL-ADXL350Z-S

• Rohs: yes
• Product: Satellite Boards
• Description/function: 3 axis accelerometer evaluation board
• Interface Type: I2C, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2 V to 3.6 V
• Factory Pack Quantity: 1
• For Use With: ADXL350

ADXL350
Trigger Mode
In trigger mode, FIFO accumulates samples, holding the latest
32 samples from measurements of the x-, y-, and z-axes. After
a trigger event occurs and an interrupt is sent to the INT1 or
INT2 pin (determined by the trigger bit in the FIFO_CTL register),
FIFO keeps the last n samples (where n is the value specified by
the samples bits in the FIFO_CTL register) and then operates in
FIFO mode, collecting new samples only when FIFO is not full.
A delay of at least 5 μs should be present between the trigger event
occurring and the start of reading data from the FIFO to allow
the FIFO to discard and retain the necessary samples. Additional
trigger events cannot be recognized until the trigger mode is
reset. To reset the trigger mode, set the device to bypass mode
and then set the device back to trigger mode. Note that the
FIFO data should be read first because placing the device into
bypass mode clears FIFO.
Retrieving Data from FIFO
The FIFO data is read through the DATAX, DATAY, and DATAZ
registers (Address 0x32 to Address 0x37). When the FIFO is in
FIFO, stream, or trigger mode, reads to the DATAX, DATAY,
and DATAZ registers read data stored in the FIFO. Each time
data is read from the FIFO, the oldest x-, y-, and z-axes data are
placed into the DATAX, DATAY, and DATAZ registers.
If a single-byte read operation is performed, the remaining
bytes of data for the current FIFO sample are lost. Therefore, all
axes of interest should be read in a burst (or multiple-byte) read
operation. To ensure that the FIFO has completely popped (that
is, that new data has completely moved into the DATAX, DATAY,
and DATAZ registers), there must be at least 5 μs between the
end of reading the data registers and the start of a new read of
the FIFO or a read of the FIFO_STATUS register (Address 0x39).
The end of reading a data register is signified by the transition
from Register 0x37 to Register 0x38 or by the CS pin going high.
For SPI operation at 1.6 MHz or less, the register addressing
portion of the transmission is a sufficient delay to ensure that
the FIFO has completely popped. For SPI operation greater than
1.6 MHz, it is necessary to deassert the CS pin to ensure a total
delay of 5 μs; otherwise, the delay will not be sufficient. The total
delay necessary for 5 MHz operation is at most 3.4 μs. This is
not a concern when using I
rate is low enough to ensure a sufficient delay between FIFO reads.
2
C mode because the communication
Rev. 0 | Page 22 of 36
SELF-TEST
The
tests its mechanical and electronic systems simultaneously.
When the self-test function is enabled (via the SELF_TEST bit
in the DATA_FORMAT register, Address 0x31), an electrostatic
force is exerted on the mechanical sensor. This electrostatic force
moves the mechanical sensing element in the same manner as
acceleration, and it is additive to the acceleration experienced
by the device. This added electrostatic force results in an output
change in the x-, y-, and z-axes. Because the electrostatic force
is proportional to V
The self-test feature of the
behavior that depends on which phase of the clock self-test is
enabled. However, the limits shown in Table 1 and Table 13
to Table 16 are valid for all potential self-test values across the
entire allowable voltage range. Use of the self-test feature at data
rates less than 100 Hz may yield values outside these limits.
Therefore, the part should be placed into a data rate of 100 Hz
or greater when using self-test.
Table 13. Self-Test Output in LSB for ±1 g, 10-bit Resolution
or any g-Range, Full Resolution
Axis
X
Y
Z
Table 14. Self-Test Output in LSB for ±2 g, 10-Bit Resolution
Axis
X
Y
Z
Table 15. Self-Test Output in LSB for ±4 g, 10-Bit Resolution
Axis
X
Y
Z
Table 16. Self-Test Output in LSB for ±8 g, 10-Bit Resolution
Axis
X
Y
Z
ADXL350
incorporates a self-test feature that effectively
Min
100
−1180
150
Min
50
−590
75
Min
25
−295
38
Min
12
−148
19
S
2
, the output change varies with V
ADXL350
also exhibits a bimodal
Max
1180
−100
1850
Max
590
−50
925
Max
295
−25
463
Max
148
−12
232
Data Sheet
S
.
Unit
LSB
LSB
LSB
Unit
LSB
LSB
LSB
Unit
LSB
LSB
LSB
Unit
LSB
LSB
LSB