MT48LC8M8A2P-75:G Micron Technology Inc, MT48LC8M8A2P-75:G Datasheet - Page 13

• Manufacturer Part Number: MT48LC8M8A2P-75:G
• Description: IC SDRAM 64MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M8A2P-75:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (8M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 8Mx8
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Definition
Mode Register
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Note:
10. Issue an AUTO REFRESH command.
11. Wait at least
12. The SDRAM is now ready for mode register programming. Because the mode register
13. Wait at least
1. Simultaneously apply power to V
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing
4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT
5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least
6. Perform a PRECHARGE ALL command.
7. Wait at least
8. Issue an AUTO REFRESH command.
9. Wait at least
The recommended power-up sequence for SDRAMs:
At this point the DRAM is ready for any valid command.
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CL, an operating mode
and a write burst mode, as shown in Figure 6 on page 15. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CL, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future
use.
compatible.
constraints specified for the clock pin.
or NOP.
through the end of this period, 1 or more COMMAND INHIBIT or NOP commands
must be applied.
All banks will complete their precharge, thereby placing the device in the all banks
idle state.
are allowed.
are allowed.
will power up in an unknown state, it should be loaded with desired bit values prior to
applying any operational command. Using the LOAD MODE REGISTER command,
program the mode register. The mode register is programmed via the MODE REGIS-
TER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is
programmed again or the device loses power. Not programming the mode register
upon initialization will result in default settings which may not be desired. Outputs
are guaranteed High-Z after the LOAD MODE REGISTER command is issued. Outputs
should be High-Z already before the LOAD MODE REGISTER command is issued.
allowed.
If desired, more than two AUTO REFRESH commands can be issued in the sequence.
After steps 9 and 10 are complete, repeat them until the desired number of AUTO
REFRESH +
t
t
t
t
t
RFC loops is achieved.
RP time; during this time NOPs or DESELECT commands must be given.
RFC time, during which only NOPs or COMMAND INHIBIT commands
RFC time, during which only NOPs or COMMAND INHIBIT commands
MRD time, during which only NOP or DESELECT commands are
13
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and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q.
64Mb: x4, x8, x16 SDRAM
Functional Description
©2000 Micron Technology, Inc. All rights reserved.