MT48LC8M8A2P-75:G Micron Technology Inc, MT48LC8M8A2P-75:G Datasheet - Page 33

• Manufacturer Part Number: MT48LC8M8A2P-75:G
• Description: IC SDRAM 64MBIT 133MHZ 54TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M8A2P-75:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (8M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Organization: 8Mx8
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 23:
PRECHARGE
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
WRITE-to-PRECHARGE
Note:
COMMAND
COMMAND
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 24 on page 34, where data n is
the last desired data element of a longer burst.
The PRECHARGE command (Figure 25 on page 34) is used to deactivate the open row in
a particular bank or the open row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
t WR @ t CLK ≥ 15ns
t WR = t CLK < 15ns
ADDRESS
ADDRESS
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
DQM
DQM
CLK
DQ
DQ
BANK a,
BANK a,
WRITE
WRITE
COL n
COL n
D
D
T0
n
n
IN
IN
n + 1
n + 1
NOP
NOP
T1
D
D
IN
IN
t
WR
PRECHARGE
(a or all)
BANK
T2
NOP
33
t
WR
TRANSITIONING DATA
PRECHARGE
(a or all)
BANK
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP) after the PRECHARGE command is issued.
t RP
NOP
NOP
T4
t RP
BANK a,
ACTIVE
ROW
NOP
T5
64Mb: x4, x8, x16 SDRAM
DON’T CARE
BANK a,
ACTIVE
ROW
NOP
T6
©2000 Micron Technology, Inc. All rights reserved.
Commands