MT48LC2M32B2P-55:G Micron Technology Inc, MT48LC2M32B2P-55:G Datasheet - Page 62

IC SDRAM 64MBIT 5.5NS 86TSOP

MT48LC2M32B2P-55:G

Manufacturer Part Number
MT48LC2M32B2P-55:G
Description
IC SDRAM 64MBIT 5.5NS 86TSOP
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT48LC2M32B2P-55:G

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
5.5ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 44:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
DQML, DQMH
COMMAND
BA0, BA1
DQM /
A0-A9
CLK
CKE
A10
DQ
Single WRITE
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Notes:
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 10ns is required between <D
3. A8 and A9 = “Don’t Care.”
t CK
to meet
T1
NOP
DISABLE AUTO PRECHARGE
t
WR.
t CMS
t CL
t DS
COLUMN m 3
WRITE
BANK
T2
D
IN
t CMH
t CH
t DH
m
t WR
62
IN
m> and the PRECHARGE command, regardless of frequency,
T3
NOP
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T4
T5
NOP
t RP
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Timing Diagrams
ACTIVE
ROW
T6
ROW
BANK
DON’T CARE

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