MT48LC4M32B2P-7:G Micron Technology Inc, MT48LC4M32B2P-7:G Datasheet - Page 34

• Manufacturer Part Number: MT48LC4M32B2P-7:G
• Description: IC SDRAM 128MBIT 143MHZ 86TSOP
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2P-7:G

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOPII
• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/8/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 175mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 26:
Burst READ/Single WRITE
Concurrent Auto Precharge
READ with Auto Precharge
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
CLOCK SUSPEND During READ Burst
Notes:
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
COMMAND
1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed BL.
READ commands access columns according to the programmed BL and sequence, just
as in the normal mode of operation (M9 = 0).
An access command to (READ or WRITE) another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
INTERNAL
ADDRESS
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (see Figure 27 on page 35).
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (see Figure 28 on page 35).
CLOCK
CKE
CLK
DQ
T0
BANK,
COL n
READ
T1
NOP
T2
NOP
D
OUT
n
34
T3
n + 1
D
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
NOP
T5
NOP
n + 2
D
OUT
DON’T CARE
T6
NOP
D
n + 3
OUT
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition