MT45W4MW16BCGB-701 IT Micron Technology Inc, MT45W4MW16BCGB-701 IT Datasheet - Page 23

• Manufacturer Part Number: MT45W4MW16BCGB-701 IT
• Description: IC PSRAM 64MB 54-VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 IT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3816748

Software Access
Figure 16:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
Load Configuration Register
Software access of the registers uses a sequence of asynchronous READ and asynchro-
nous WRITE operations. The contents of the configuration registers can be modified,
and all registers can be read using the software sequence.
The configuration registers are loaded using a four-step sequence consisting of two
asynchronous READ operations followed by two asynchronous WRITE operations (see
Figure 16). The read sequence is virtually identical except that an asynchronous READ is
performed during the fourth operation (see Figure 17 on page 24). The address used
during all READ and WRITE operations is the highest address of the CellularRAM device
being accessed (3FFFFFh for 64Mb); the contents of this address are not changed by
using this sequence.
The data value presented during the third operation (WRITE) in the sequence defines
whether the BCR, RCR, or the DIDR is to be accessed. If the data is 0000h, the sequence
will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is
0002h, the sequence will access the DIDR. During the fourth operation, DQ[15:0]
transfer data into or out of bits 15:0 of the registers.
The use of the software sequence does not affect the ability to perform the standard
(CRE-controlled) method of loading the configuration registers. However, the software
nature of this access mechanism eliminates the need for CRE. If the software mecha-
nism is used, CRE can simply be tied to V
purposes is no longer required.
LB#/UB#
Address
Data
WE#
OE#
CE#
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
Address
(MAX)
XXXXh
READ
Address
(MAX)
READ
XXXXh
23
RCR: 0000h
BCR: 0001h
Address
WRITE
(MAX)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SS
. The port line often used for CRE control
CR value
Address
WRITE
(MAX)
Don't Care
in
©2005 Micron Technology, Inc. All rights reserved.
Registers