MT45W4MW16BCGB-701 IT Micron Technology Inc, MT45W4MW16BCGB-701 IT Datasheet - Page 25

• Manufacturer Part Number: MT45W4MW16BCGB-701 IT
• Description: IC PSRAM 64MB 54-VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BCGB-701 IT

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3816748

Bus Configuration Register
Figure 18:
PDF: 09005aef8247bd51/Source: 09005aef8247bd83
64mb_burst_cr1_5_p25z_133mhz__2.fm - Rev. F 9/07 EN
All must be set to “0”
BCR[19]
A[21:20]
Reserved
21–20
0
1
0
BCR[15]
Register
0
1
BCR[18]
Select
A[19:18]
Bus Configuration Register Definition
19–18
0
0
1
Must be set to “0”
BCR[13]
BCR[14]
0
0
0
0
1
1
1
1
0
1
Operating Mode
Asynchronous access mode (default)
Notes:
Synchronous burst access mode
Reserved
Register Select
Select RCR
Select BCR
Select DIDR
17–16
A[17:16]
BCR[12] BCR[11]
BCR[10]
0
0
1
1
0
0
1
1
Initial Access Latency
Fixed
Variable (default)
Operating
0
1
Mode
15
The BCR defines how the CellularRAM device interacts with the system memory bus.
Page mode operation is enabled by a bit contained in the RCR. Figure 18 defines the
control bits in the BCR. At power-up, the BCR is set to 9D1Fh.
The BCR is accessed with CRE HIGH and A[19:18] = 10b or through the register access
software sequence with DQ = 0001h on the third cycle.
1. Burst wrap and length apply both to READ and WRITE operations.
A15
0
1
0
1
0
1
0
1
WAIT Polarity
Active LOW
Active HIGH (default)
Latency
Initial
Latency Counter
Code 8
Code 1–Reserved
Code 2
Code 3 (Default)
Code 4
Code 5
Code 6
Code 7–Reserved
14
A14
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.5 Memory
A13
13 12 11
Counter
Latency
A12 A11 A10
Polarity
WAIT
10
Must be set to “0”
Reserved
9
A9
Configuration (WC)
25
BCR[8]
WAIT
0
1
8
A8
Must be set to “0”
Asserted one data cycle before delay (default)
WAIT Configuration
Asserted during delay
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Reserved
7
A7
BCR[5]
0
0
1
1
Setting is ignored
(Default to “0”)
BCR[3]
0
1
Reserved
BCR[4]
BCR[2]
0
1
0
1
6
A6
0
0
0
1
1
Burst wraps within the burst length
Burst no wrap (default)
Burst Wrap (Note 1)
Others
BCR[1] BCR[0]
Drive Strength
1/2 (default)
1/4
Reserved
Full
0
1
1
0
1
Drive Strength
5
A5
1
0
1
0
1
©2005 Micron Technology, Inc. All rights reserved.
Burst Length (Note 1)
4 words
8 words
16 words
32 words
Continuous burst (default)
Reserved
4
A4
Wrap (BW)
Burst
3
A3
Registers
1
Length (BL)
2
A2 A1 A0
Burst
1
0
1