MT48H16M32LFCM-6:B TR Micron Technology Inc, MT48H16M32LFCM-6:B TR Datasheet
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MT48H16M32LFCM-6:B TR
Specifications of MT48H16M32LFCM-6:B TR
Related parts for MT48H16M32LFCM-6:B TR
MT48H16M32LFCM-6:B TR Summary of contents
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Mobile Low-Power SDR SDRAM MT48H32M16LF – 8 Meg banks MT48H16M32LF/LG – 4 Meg banks Features • 1.7–1.95V DD DDQ • Fully synchronous; all signals registered on positive edge of ...
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Figure 1: 512Mb Mobile LPSDR Part Numbering MT Micron Technology Product Family 48 = Mobile SDR SDRAM Operating Voltage H = 1.8V/1.8V Configuration 32 Meg Meg x 32 Addressing LF = Mobile standard addressing LG = Reduced ...
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Contents General Description ......................................................................................................................................... 8 Functional Block Diagram ................................................................................................................................ 9 Ball Assignments and Descriptions ................................................................................................................. 10 Package Dimensions ...................................................................................................................................... 13 Electrical Specifications .................................................................................................................................. 15 Absolute Maximum Ratings ........................................................................................................................ 15 Electrical Specifications – I Parameters ........................................................................................................ 17 DD Electrical Specifications – ...
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Rev. D, Production – 2/09 ........................................................................................................................... 85 Rev. C, Production – 12/08 .......................................................................................................................... 85 Rev. B, Preliminary – 4/08 ........................................................................................................................... 85 Rev. A, Advance – 10/07 .............................................................................................................................. 85 Revision History for Commands, Operations, and Timing Diagrams ............................................................. 86 Update – ...
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List of Tables Table 1: Configuration Addressing ................................................................................................................... 1 Table 2: Key Timing Parameters ...................................................................................................................... 1 Table 3: VFBGA Ball Descriptions .................................................................................................................. 12 Table 4: Absolute Maximum Ratings .............................................................................................................. 15 Table 5: DC Electrical Characteristics and Operating Conditions ..................................................................... 15 ...
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List of Figures Figure 1: 512Mb Mobile LPSDR Part Numbering .............................................................................................. 2 Figure 2: Functional Block Diagram ................................................................................................................. 9 Figure 3: 54-Ball VFBGA (Top View) ............................................................................................................... 10 Figure 4: 90-Ball VFBGA (Top View) ............................................................................................................... 11 Figure 5: 54-Ball VFBGA (8mm ...
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Figure 51: Clock Suspend During READ Burst ................................................................................................ 83 Figure 52: Clock Suspend Mode ..................................................................................................................... 84 PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM 7 Micron Technology, Inc. reserves ...
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... General Description The 512Mb Mobile LPSDR is a high-speed CMOS, dynamic random-access memory con- taining 536,870,912-bits internally configured as a quad-bank DRAM with a syn- chronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1K columns by 16 bits. Each of the x32’ ...
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... Functional Block Diagram BA1 BA0 Bank Bank3 Bank2 Bank1 Bank0 memory array Data output n register Data input n register Column decoder Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved DQM ...
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Ball Assignments and Descriptions Figure 3: 54-Ball VFBGA (Top View DQ14 C DQ12 D DQ10 E DQ8 F UDQM The E2 pin must be connected to ...
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Figure 4: 90-Ball VFBGA (Top View DQ26 DQ24 B DQ28 V DDQ C V DQ27 SSQ D V DQ29 SSQ E V DQ31 DDQ F V DQM3 CLK CKE K ...
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... Address inputs: Addresses are sampled during the ACTIVE command (row) and READ/WRITE command [column); column address A[9:0] (x16); with A10 defining auto precharge] to select one location out of the memory array in the respective bank. A10 is sampled during a PRE- CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 ...
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Package Dimensions Figure 5: 54-Ball VFBGA (8mm x 9mm) Seating plane A 0.1 A 54X Ø0.45 Solder ball diameter refers to post reflow condition. The pre reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.2 6.4 0.8 ...
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Figure 6: 90-Ball VFBGA (10mm x 13mm) Seating plane A 0.12 A 90X Ø0.45 Solder ball material: SAC105. Dimensions apply to solder balls post- reflow on Ø0 SMD ball pads. 11.2 CTR 0.8 TYP 1. 1. All ...
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Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in ...
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Table 6: Capacitance Note 1 applies to all parameters and conditions Parameter Input capacitance: CLK Input capacitance: All other input-only balls Input/output capacitance This parameter is sampled. V Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: ...
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Electrical Specifications – I Table 7: I Specifications and Conditions (x16) DD Note 1 applies to all parameters and conditions; V Parameter/Condition Operating current: Active mode; Burst = 1; READ or WRITE; (MIN) Standby current: Power-down mode; All banks idle; ...
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Table 9: I Specifications and Conditions (x16 and x32) DD7 Notes and 10 apply to all parameters and conditions; V Parameter/Condition Self refresh t t CKE = LOW (MIN); Address and control inputs are ...
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Figure 7: Typical Self Refresh Current vs. Temperature 700 650 600 550 500 450 400 350 300 250 200 150 100 -40 -35 -30 -25 -20 -15 -10 -5 PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg ...
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Electrical Specifications – AC Operating Conditions Table 10: Electrical Characteristics and Recommended AC Operating Conditions Notes 1–5 apply to all parameters and conditions AC Characteristics Parameter Access time from CLK (positive edge) Address hold time Address setup time CLK high-level ...
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Table 11: AC Functional Characteristics Notes 1–5 apply to all parameters and conditions Parameter Last data-in to burst STOP command READ/WRITE command to READ/WRITE command Last data-in to new READ/WRITE command CKE to clock disable or power-down entry mode Data-in ...
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For auto precharge mode, the precharge timing budget ( 11. CLK must be toggled a minimum of two times during this period. 12. Required clocks are specified by JEDEC functionality and are not dependent on any tim- 13. Timing ...
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Output Drive Characteristics Table 12: Target Output Drive Characteristics (Full Strength) Notes 1–2 apply to all parameters and conditions; characteristics are specified under best and worst process variations/con- ditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 ...
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Table 13: Target Output Drive Characteristics (Three-Quarter Strength) Notes 1 and 2 apply to all parameters and conditions; characteristics are specified under best and worst process variations/ conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 ...
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Table 14: Target Output Drive Characteristics (One-Half Strength) Notes 1–3 apply to all parameters and conditions; characteristics are specified under best and worst process variations/con- ditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 ...
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... Precharging one bank while accessing one of the other three banks will hide the precharge cycles. The device is designed to operate in 1.8V memory systems. An auto refresh mode is pro- vided, along with power-saving, power-down, and deep power-down modes. All inputs and outputs are LVTTL-compatible ...
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Commands The following table provides a quick reference of available commands, followed by a written description of each command. Additional Truth Tables (Table 16 (page 33), Table 17 (page 35), and Table 18 (page 37)) provide current state/next state informa- ...
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COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the device, regardless of whether the CLK signal is enabled. The device is effectively de- selected. Operations already in progress are not affected. NO OPERATION (NOP) The ...
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READ The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided selects the starting column location. The value on input A10 ...
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... Input data appearing on the DQ is written to the memory array, subject to the DQM input logic level appearing coincident with the data given DQM signal is registered LOW, the corresponding data is written to memory ...
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PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( whether one or all ...
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... DEEP POWER-DOWN The DEEP POWER-DOWN (DPD) command is used to enter deep power-down mode, achieving maximum power reduction by eliminating the power to the memory array. To enter DPD, all banks must be idle. While CKE is LOW, hold CS# and WE# LOW, and hold RAS# and CAS# HIGH at the rising edge of the clock. To exit DPD, assert CKE HIGH. ...
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Truth Tables Table 16: Truth Table – Current State Bank n, Command to Bank n Notes 1–6 apply to all parameters and conditions Current State CS# Any H L Idle Row active Read ...
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The following states must not be interrupted by any executable command; COMMAND 6. All states and sequences not shown are illegal or reserved. 7. Not bank specific; requires that all banks are idle. 8. Does not affect the state ...
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Table 17: Truth Table – Current State Bank n, Command to Bank m Notes 1–6 apply to all parameters and conditions Current State CS# Any H L Idle X Row activating, active precharging Read L ...
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AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be is BURST TERMINATE command cannot be issued to another bank; it applies to the bank 6. All states and sequences not shown are illegal or ...
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Table 18: Truth Table – CKE Notes 1–4 apply to all parameters and conditions Current State CKE n-1 Power-down L Self refresh Clock suspend Deep power-down Power-down L Deep power-down Self refresh Clock suspend All banks idle H All banks ...
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Initialization Low-power SDRAM devices must be powered up and initialized in a predefined man- ner. Using initialization procedures other than those specified may result in undefined operation. After power is simultaneously applied to V ble (a stable clock is defined ...
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Figure 12: Initialize and Load Mode Register CLK ( ( ) ) CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ) ) ...
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Mode Register The mode register defines the specific mode of operation, including burst length (BL), burst type, CAS latency (CL), operating mode, and write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and retains the ...
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Burst Length Read and write accesses to the device are burst oriented, and the burst length (BL) is programmable. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE ...
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Table 19: Burst Definition Table Burst Length Starting Column Address Continuous n = A0–An/9/8 ...
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CAS Latency The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks READ command ...
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Extended Mode Register The extended mode register (EMR) controls additional functions beyond those control- led by the mode register. These additional functions include TCSR, PASR, and output drive strength. The EMR is programmed via the LMR command (BA1 = 1, ...
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... Partial-Array Self Refresh For further power savings during self refresh, the partial-array self refresh (PASR) fea- ture enables the controller to select the amount of memory to be refreshed during self refresh. The refresh options are: • Full array: banks and 3 • One-half array: banks 0 and 1 • ...
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Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row ...
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READ Operation READ bursts are initiated with a READ command, as shown in Figure 9 (page 29). The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst ...
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Figure 17: Consecutive READ Bursts Command Address Command Address 1. Each READ command can be issued to any bank. DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 ...
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Figure 18: Random READ Accesses Command Address Command Address 1. Each READ command can be issued to any bank. DQM is LOW. Note: Data from any READ burst can be truncated with a subsequent WRITE command, and data from a ...
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 19 (page 50) shows where, due to the clock cycle frequency, ...
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Figure 20: READ-to-WRITE With Extra Clock Cycle DQM Command Address The READ command can be issued to any bank, and the WRITE command can be Note: Figure 21: READ-to-PRECHARGE Command Address Command Address 1. DQM is ...
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Continuous-page READ bursts can be truncated with a BURST TERMINATE command and fixed-length READ bursts can be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before ...
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Figure 23: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto precharge Row ...
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Figure 24: READ Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row Column ...
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Figure 25: READ – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto precharge A10 ...
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WRITE Operation WRITE bursts are initiated with a WRITE command, as shown in Figure 10 (page 30). The starting column and bank addresses are provided with the WRITE command and auto precharge is either enabled or disabled for that access. ...
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Figure 27: WRITE-to-WRITE Command Address 1. DQM is LOW. Each WRITE command may be issued to any bank. Note: Data for any WRITE burst can be truncated with a subsequent READ command, and data for a fixed-length WRITE burst can ...
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Figure 28: Random WRITE Cycles Command Address Note: 1. Each WRITE command can be issued to any bank. DQM is LOW. Figure 29: WRITE-to-READ Command Address 1. The WRITE command can be issued to any bank, and the READ command ...
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Figure 30: WRITE-to-PRECHARGE Command Address Command Address 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two. Note: Fixed-length WRITE bursts can be truncated with the ...
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Figure 31: Terminating a WRITE Burst Command Address 1. DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM CLK BURST NEXT WRITE TERMINATE ...
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Figure 32: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Column ...
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Figure 33: WRITE – Continuous Page Burst CLK CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Row A10 t ...
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Figure 34: WRITE – DQM Operation CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Row A10 ...
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PRECHARGE Operation The PRECHARGE command (see Figure 11 (page 31)) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a sub- sequent row access some ...
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WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after registered. The last valid data ...
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Figure 36: READ With Auto Precharge Interrupted by a WRITE CLK Command Page Bank n active Internal States Bank m Address 1 DQM DQ Note: 1. DQM is HIGH prevent D PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H ...
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Figure 37: READ With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Row Address Enable auto precharge Row ...
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Figure 38: READ Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row A10 Row Disable auto precharge t ...
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Figure 39: Single READ With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row A10 Row ...
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Figure 40: Single READ Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row A10 Row ...
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Figure 41: WRITE With Auto Precharge Interrupted by a READ CLK Command Bank n Internal States Bank m Address DQ 1. DQM is LOW. Note: Figure 42: WRITE With Auto Precharge Interrupted by a WRITE CLK Command Bank n Internal ...
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Figure 43: WRITE With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row Column ...
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Figure 44: WRITE Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP t CMS DQM Address Row Column ...
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Figure 45: Single WRITE With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Address Row Enable auto precharge A10 Row ...
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Figure 46: Single WRITE Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH Command ACTIVE NOP DQM Row Address A10 Row Disable auto precharge ...
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AUTO REFRESH Operation The AUTO REFRESH command is used during normal operation of the device to refresh the contents of the array. This command is nonpersistent must be issued each time a refresh is required. All active banks ...
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Figure 47: Auto Refresh Mode T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH Command PRECHARGE DQM Address All banks A10 Single bank BA0, BA1 Bank(s) High Precharge ...
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SELF REFRESH Operation The self refresh mode can be used to retain data in the device, even when the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The SELF ...
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Figure 48: Self Refresh Mode T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH Command PRECHARGE NOP DQM Address All banks A10 Single bank BA0, BA1 Bank(s) High ...
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Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN- HIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down ...
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... Deep Power-Down Deep power-down mode is a maximum power-saving feature achieved by shutting off the power to the entire device memory array. Data on the memory array will not be re- tained after deep power-down mode is executed. Deep power-down mode is entered by having all banks idle, with CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW ...
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Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing the synchronous logic. For each positive clock edge on which ...
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Figure 51: Clock Suspend During READ Burst CLK CKE Internal clock Command Address DQ 1. For this example greater, and DQM is LOW. Note: PDF: 09005aef82ea3742 512mb_mobile_sdram_y47m.pdf – Rev. H 12/09 EN 512Mb: ...
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Figure 52: Clock Suspend Mode CLK t CKS CKE t CKS t CKH t CMS t CMH Command READ NOP t CMS t CMH DQM Address Column ...
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Revision History Rev. H, Production – 12/09 • Changed Rev. G, Production – 8/09 • Updated format. Rev. F, Production – 4/09 • AC Functional Characteristics table: Updated note 9. Rev. E, Production – 3/09 • Typical I Rev. D, ...
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Revision History for Commands, Operations, and Timing Diagrams Update – 10/08 • Deep Power-Down: Added description for exiting DPD. Update – 7/08 • Updated address/data range presentation to industry-standard presentation. • Replaced MODE REGISTER SET with LMR as appropriate. • ...