IS42S32800B-6BL ISSI, Integrated Silicon Solution Inc, IS42S32800B-6BL Datasheet - Page 6

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IS42S32800B-6BL

Manufacturer Part Number
IS42S32800B-6BL
Description
IC SDRAM 256MBIT 166MHZ 90BGA
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet

Specifications of IS42S32800B-6BL

Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (8Mx32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
90-BGA
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS42S32800B-6BL
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS42S32800B-6BL-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS42S32800B-6BLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS42S32800B-6BLI-TR
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
IS42S32800B
6
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth
table for the operation commands.
Note:
1. V =Valid,X =Don ’t care,L =Logic low,H =Logic high
2. CKEn signal is input level when commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1,2,4,8,and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
6. DQM0-3
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and Auto Precharge Active
Read
Read and Autoprecharge
Mode Register
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Clock Suspend Mode Entry Active
Power Down Mode Entry
Clock Suspend Mode Exit Active
Power Down Mode Exit
Data Write/Output Enable Active
Data Mask/Output Disable Active
CKEn-1 signal is input level one clock cycle before the commands are provided.
When this command is asserted in the burst cycle,device state is clock suspend mode.
State
Any
Set Idle
Any
Idle
Any
Active
Active
Active
Any
Active
Idle
Idle
Idle
(SelfRefresh)
Any
Any
(PowerDown)
Table 2.Truth Table (Note (1),(2))
(5)
(3)
(4)
(3)
(3)
(3)
(3)
CKEn-1 CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
(6)
BS0,1
V
V
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
A10
Row address
L
H
L
H
L
H
OP code
X
X
X
X
X
X
X
X
X
X
X
X
Column
address
(A0 ~A8)
Column
address
(A0 ~A8)
A11,A9-0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Integrated Silicon Solution, Inc.
L
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
07/21/09
Rev. F

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