IS42S32800B-6BL ISSI, Integrated Silicon Solution Inc, IS42S32800B-6BL Datasheet - Page 7

• Manufacturer Part Number: IS42S32800B-6BL
• Description: IC SDRAM 256MBIT 166MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32800B-6BL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-BGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 180mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S32800B
I
Commands
Integrated Silicon Solution, Inc.
Rev. F
07/21/09
2
1
BankPrecharge command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Bank,A10 =”L”)
The BankPrecharge command precharges the bank disignated by BS0,1 signal.The
precharged bank is switched from the active state to the idle state.This command can be asserted anytime after
tRAS(min.)is satisfied from the BankActivate command in the desired bank.The maximum time any bank can be
active is specified by tRAS(max.).Therefore,the precharge function must be performed in any active bank within
tRAS(max.).At the end of precharge,the precharged bank is still in the idle state and is ready to be activated again.
ADDRESS
C O M M A N D
CLK
(RAS#=”L”,CAS#=”H”,WE#=”H”,BS =Bank,A0-A11 =Row Address)
The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the
row address on A0 to A11 at the time of this command,the selected row access is initiated.The read or write
operation in the same bank can occur after a time delay of tRCD(min.)from the time of bank activation.A
subsequent BankActivate command to a different row in the same bank can only be issued after the previous
active row has been precharged (refer to the following figure).The minimum time interval between successive
BankActivate commands to the same bank is defined by tRC(min.).The SDRAM has four internal banks on the
same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back
activation of the four banks.tRRD(min.)specifies the minimum time required between activating different banks.
After this command is used,the Write command and the Block Write command perform the no mask write
operation.
BankActivate
:"H" or "L"
Row Addr.
Activate
Bank A
Bank A
T0
RAS# - CAS# delay (
T1
NOP
Bank
T2
NOP
t
RCD
)
AutoPrecharge
Col Addr.
T3
R/W A with
Bank A
RAS# Cycle time (
..............
..............
..............
t
RC
)
Auto Precharge
Row Addr.
Tn+3
Activate
Begin
Bank B
Bank B
RAS#- RAS# delay time (
Tn+4
NOP
Tn+5
NOP
t
RRD
)
Row Addr.
I
Activate
Bank A
Bank A
Tn+6
®
7