IS64WV51216BLL-10MA3 ISSI, Integrated Silicon Solution Inc, IS64WV51216BLL-10MA3 Datasheet - Page 16

• Manufacturer Part Number: IS64WV51216BLL-10MA3
• Description: IC SRAM 8MBIT 10NS 48MBGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS64WV51216BLL-10MA3

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 8M (512K x 16)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-MBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS61WV51216ALL
IS61WV51216BLL
IS64WV51216BLL
AC WAVEFORMS
WRITE CYCLE NO. 4
16
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
any can be deasserted to terminate the Write. The
ADDRESS
UB, LB
D
OUT
WE
D
OE
CE
IN
LOW
DATA UNDEFINED
(LB, UB Controlled, Back-to-Back Write)
t
HZWE
ADDRESS 1
t
SA
t
,
t
SD
HA
t
t
SA
WORD 1
WC
,
t
t
PBW
SD
HIGH-Z
, and
DATA
VALID
t
IN
HD
timing is referenced to the rising or falling edge of the signal that terminates the Write.
t
t
HD
HA
t
SA
ADDRESS 2
Integrated Silicon Solution, Inc. — www.issi.com
(1,3)
t
t
SD
WC
WORD 2
t
PBW
DATA
VALID
IN
t
LZWE
t
HD
t
HA
UB_CEWR4.eps
10/01/09
Rev. F