MT46H64M32L2CG-6 IT:A TR Micron Technology Inc, MT46H64M32L2CG-6 IT:A TR Datasheet

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MT46H64M32L2CG-6 IT:A TR

Manufacturer Part Number
MT46H64M32L2CG-6 IT:A TR
Description
IC DDR SDRAM 2GBIT 152VFBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT46H64M32L2CG-6 IT:A TR

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
2G (64M x 32)
Speed
166MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
152-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Mobile LPDDR (only)
152-Ball Package-on-Package (PoP) TI-OMAP™
MT46HxxxMxxLxCG
MT46HxxxMxxLxKZ
Features
• V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data—one mask
• Programmable burst lengths (BLs): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control self refresh
• Partial-array self refresh (PASR)
• Deep power-down (DPD)
• STATUS REGISTER READ (SRR) supported
• Selectable output drive strength (DS)
• Clock stop capability
• 64ms refresh
Table 1:
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
Architecture
Configuration
Refresh count
Row addressing
Column addressing
architecture; 2 data accesses per clock cycle
aligned with data for WRITEs
per byte
rate
DD
/
V
DDQ
= 1.70–1.95V
Configuration Addressing
Notes:
x 4 banks x 4 die
128 Meg x 32
16K (A[13:0])
16 Meg x 16
1K (A[9:0])
1. Quad die stack. Each CS configured with two x16 die connected in parallel to make up a 32-bit-
8K
wide bus.
1
2
x 4 banks x 2 die
64 Meg x 32
1
8K (A[12:0])
1K (A[9:0])
8 Meg x 32
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
8K
1
Options
• V
• Configuration
• Device version
• Plastic “green” package
• Timing – cycle time
• Operating temperature range
Notes: 1. BL 16: contact factory for availability.
– 1.8V/1.8V
– 128 Meg x 32 (16 Meg x 16 x 4 banks x 4)
– 64 Meg x 32 (8 Meg x 32 x 4 banks x 2)
– 32 Meg x 32 (8 Meg x 32 x 4 banks)
– 16 Meg x 32 (4 Meg x 32 x 4 banks)
– Single die, standard addressing
– 2-die stack, standard addressing
– 4-die stack, standard addressing
– 152-ball VFBGA (14 x 14 x 1.0mm)
– 152-ball VFBGA (14 x 14 x 1.2mm)
– 5ns @ CL = 3
– 5.4ns @ CL = 3
– 6ns @ CL = 3
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
/
2. Contact factory for remapped SRR output.
V
DDQ
32 Meg x 32
8K (A[12:0])
1K (A[9:0])
8 Meg x 32
x 4 banks
8K
©2008 Micron Technology, Inc. All rights reserved.
16 Meg x 32
8K (A[12:0])
512 (A[8:0])
4 Meg x 32
x 4 banks
8K
Features
Marking
128M32
64M32
32M32
16M32
None
-54
CG
KZ
LF
L2
L4
-5
-6
IT
H

Related parts for MT46H64M32L2CG-6 IT:A TR

MT46H64M32L2CG-6 IT:A TR Summary of contents

Page 1

Mobile LPDDR (only) 152-Ball Package-on-Package (PoP) TI-OMAP™ MT46HxxxMxxLxCG MT46HxxxMxxLxKZ Features • 1.70–1.95V / DD DDQ • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; 2 data accesses per clock ...

Page 2

Part Numbering Information – 152-Ball PoP Micron Figure 1: Marketing Part Number Example MT Micron Technology Product Family 46 = LPDDR-SDRAM Operating Voltage H = 1.8V/1.8V Configuration 128 Meg Meg Meg ...

Page 3

... MT46H32M32LFCG-54 IT:A MT46H32M32LFCG-6:A MT46H32M32LFCG-6 IT:A MT46H64M32L2CG-5:A MT46H64M32L2CG-5 IT:A MT46H64M32L2CG-54:A MT46H64M32L2CG-54 IT:A MT46H64M32L2CG-6:A MT46H64M32L2CG-6 IT:A MT46H128M32L4KZ-6 IT ES:A Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanu- meric code is used ...

Page 4

... Micron 152-ball packaged Mobile Low-Power DDR SDRAM (LPDDR) devices contain either 1Gb LPDDR or 512Mb LPDDR die. The 1Gb LPDDR die is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits internally configured as a quad-bank DRAM. Each of the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits. ...

Page 5

Ball Assignments and Descriptions Figure 3: 152-Ball VFBGA Ball Assignments DM1 DQ13 DQ15 DDQ NC NC DQ6 DQ7 V DQ9 B DDQ C V DQS0 SSQ D DQ3 DQ5 DQ0 DQ1 ...

Page 6

Table 3: Ball Assignments Symbol Type A[13:0] Input Address inputs: Specify the row or column address. Also used to load the mode registers. The maximum address is determined by density and configuration. Consult the LPDDR product data sheet for the ...

Page 7

Electrical Specifications Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated ...

Page 8

Device Diagrams Figure 4: 152-Ball VFBGA Functional Block Diagram (non-Quad Die) RAS# CAS# WE# Address, BA0, BA1 PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) CS# CK CK# CKE LPDDR 8 Device ...

Page 9

Figure 5: 152-Ball VFBGA Functional Block Diagram, Quad Die CS0# CKE0 RAS# CAS# Address, BA0, BA1 CS1# CKE1 RAS# CAS# Address, BA0, BA1 PDF: 09005aef833913f1/Source: 09005aef833913d6 ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN 152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP) CK ...

Page 10

Package Dimensions Figure 6: 152-Ball VFBGA Package, 1.0mm (Package Code: CG) Seating plane A 0.1 A 152X Ø0.46 Solder ball material: SAC105. Dimensions apply to solder balls post- reflow on Ø0. ...

Page 11

Figure 7: 152-Ball VFBGA Package, 1.2mm (Package Code: KZ) Seating plane A 0.1 A 152X Ø0.46 Solder ball material: SAC105. Dimensions apply to solder balls post- reflow on Ø0.35 SMD ball pads ...

Page 12

Revision History Rev. E, Production ...

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