MT46H64M32L2CG-6 IT:A TR Micron Technology Inc, MT46H64M32L2CG-6 IT:A TR Datasheet - Page 6

• Manufacturer Part Number: MT46H64M32L2CG-6 IT:A TR
• Description: IC DDR SDRAM 2GBIT 152VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H64M32L2CG-6 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 2G (64M x 32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 152-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3:
Table 4:
PDF: 09005aef833913f1/Source: 09005aef833913d6
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
CKE0, CKE1
CS0#, CS1#
BA0, BA1
DQ[31:0]
DQS[3:0]
Symbol
CK, CK#
DM[3:0]
A[13:0]
Symbol
CAS#
RAS#
V
RFU
WE#
V
V
DNU
TQ
DDQ
V
SSQ
NC
DD
SS
1
Ball Assignments
Output Temperature sensor output: TQ HIGH when LPDDR T
Non-Device-Specific Ball Assignments
output
output
Supply
Supply
Supply
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Type
Supply
Type
–
–
–
Notes:
Address inputs: Specify the row or column address. Also used to load the mode registers. The
maximum address is determined by density and configuration. Consult the LPDDR product data
sheet for the maximum address for a given density and configuration. Unused address pins become
RFU.
Bank address inputs: Specify one of the 4 banks.
Column select: Specifies the command to execute.
CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are
sampled and referenced on the crossing of the rising edge of CK with the falling edge of CK#.
Clock enable.
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products, and is considered RFU for single products.
Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products, and is considered RFU for single products.
Data mask: Determines which bytes are written during WRITE operations.
Row select: Specifies the command to execute.
Write enable: Specifies the command to execute.
Data bus: Data inputs/outputs.
Data strobe: Coordinates read/write transfers of data; one DQS per DQ byte.
V
V
V
Reserved for future use.
DD
DDQ
SSQ
V
Do not use: Must be grounded or left floating.
No connect: Not internally connected.
SS
: LPDDR power supply.
1
: LPDDR I/O ground.
: Shared ground.
1. Balls marked RFU may or may not be connected internally. These balls should not be used.
: LPDDR I/O power supply.
Contact factory for details.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
6
Description
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
J
exceeds 85°C.
©2008 Micron Technology, Inc. All rights reserved.