MT46V64M16TG-6T:A TR Micron Technology Inc, MT46V64M16TG-6T:A TR Datasheet
MT46V64M16TG-6T:A TR
Specifications of MT46V64M16TG-6T:A TR
Related parts for MT46V64M16TG-6T:A TR
MT46V64M16TG-6T:A TR Summary of contents
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DDR SDRAM MT46V256M4 – 64 Meg Banks MT46V128M8 – 32 Meg Banks MT46V64M16 – 16 Meg Banks Features • +2.5V ±0.2V +2.5V ±0.2V ...
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Table 2: Addressing Parameter Configuration Refresh count Row address Bank address Column address Table 3: Speed Grade Compatibility Marking PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600 (2-2-2) Yes -5B – -6T – -75 -5B Figure 1: ...
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Table of Contents State Diagram ...
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State Diagram Figure 2: Simplified State Diagram Power applied Note: This diagram represents operations within a single bank only and does not capture concur- rent operations in other banks. PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core1.fm - 1Gb DDR: Rev. I, Core DDR: ...
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... A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock (CK and CK#) ...
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... Functional Block Diagrams The 1Gb DDR SDRAM is a high-speed CMOS, dynamic random access memory containing 1,073,741,824 bits internally configured as a 4-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram CKE CK# CK Control CS# logic WE# CAS# RAS# Refresh 13 counter Mode registers 16 14 A0–A13, ...
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... Column- 10 address 11 counter/ latch 1 Bank 2 Bank 1 Refresh 13 counter Row- Bank 0 14 row- address Bank 0 MUX address memory 16,384 latch array 14 & (16,384 x 512 x 32) decoder SENSE AMPLIFIERS (16,384) I/O gating 2 DM mask logic Bank control logic 2 512 Column decoder Column- ...
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Pin Assignments and Descriptions Figure 6: 66-pin TSOP Pin Assignments (Top View DQ0 DQ1 ...
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... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...
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Table 4: Pin Descriptions (continued) TSOP Numbers Symbol 34, 48 12, 52, 58 REF 14, 25, 43 10, 13, 14, NC 16, 20, 25, 43, 53, ...
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Package Dimensions Figure 7: 66-Pin Plastic TSOP (400 mil) 22.22 ± 0.08 0.65 TYP 0.32 ± .075 TYP Pin #1 ID Notes: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion ...
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Electrical Specifications – I Table 5: I Specifications and Conditions (x4, x8) DD Notes 1–5, 11, 13, 15, 47 apply to the entire table; Notes appear on page 26–31; See also Table 7 on page 14 +2.6V ...
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Table 6: I Specifications and Conditions (x16) DD Notes 1–5, 11, 13, 15, 47 apply to the entire table; Notes appear on page 26–31; See also Table 7 on page 14 +2.6V ±0.1V 0°C ≤ ...
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Table 7: I Test Cycle Times DD Values reflect number of clock cycles for each test Speed Clock Cycle I Test Grade Time -75 7.5ns DD -6T 6.0ns -5B 5.0ns I 1 -75 7.5ns DD -6T 6.0ns ...
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Electrical Specifications – DC and AC Stresses greater than those listed in Table 8 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above ...
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Table 10: DC Electrical Characteristics and Operating Conditions (-6T, -75) Notes: 1–5, 17 apply to the entire table; Notes appear on page 26; V Parameter/Condition Supply voltage I/O supply voltage I/O reference voltage I/O termination voltage (system) Input high (logic ...
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Figure 8: Input Voltage Waveform Transmitter Notes Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: ...
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Table 12: Clock Input Operating Conditions Notes: 1–5, 16, 17, 31 apply to the entire table; Notes appear on page 26; 0°C ≤ T ≤ +70° Parameter/Condition Clock input mid-point voltage: CK and CK# Clock input voltage ...
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Table 13: Capacitance (x4, x8 TSOP) Note: 14 applies to the entire table; Notes appear on page 26 Parameter Delta input/output capacitance: DQ0–DQ3 (x4), DQ0–DQ7 (x8) Delta input capacitance: Command and address Delta input capacitance: CK, CK# Input/output capacitance: DQ, ...
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Table 15: Electrical Characteristics and Recommended AC Operating Conditions (-5B) Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 15: Electrical Characteristics and Recommended AC Operating Conditions (-5B) (continued) Notes 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26; 0°C ≤ T ≤ +70° Characteristics Parameter Write recovery time Internal ...
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Table 16: Electrical Characteristics and Recommended AC Operating Conditions (-6T) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 16: Electrical Characteristics and Recommended AC Operating Conditions (-6T) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26; 0°C ≤ T ≤ +70° Characteristics Parameter DQS write postamble Write ...
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Table 17: Electrical Characteristics and Recommended AC Operating Conditions (-75) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26; 0°C ≤ T ≤ +70° Characteristics Parameter Access window of DQ from ...
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Table 17: Electrical Characteristics and Recommended AC Operating Conditions (-75) (continued) Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26; 0°C ≤ T ≤ +70° Characteristics Parameter Write recovery time Internal ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and the device operation are guaranteed for the full voltage range specified. 3. Outputs (except for I Output ...
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The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK REF 17. Inputs are not recognized as valid until ...
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CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured differentially). Figure 10: Derating Data Valid Window ( 3.0ns 2.5ns 2.0ns 1.5ns 1.0ns 32. DQ and DM input slew rates must not deviate from DQS ...
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The driver pull-up current variation within nominal limits of voltage and temper- 38e. The full ratio variation of MAX to MIN pull-up and pull-down current should be 38f. The full ratio variation of the nominal pull-up to pull-down current ...
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The driver pull-up current variation, within nominal voltage and temperature 39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should 39f. The full ratio variation of the nominal pull-up to pull-down current should be Figure 13: ...
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RPST end point and but specify when the device output is no longer driving ( t ( RPRE). 45. During initialization, V Alternatively, V provided a minimum of 42Ω of series resistance is used between the V the ...
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Table 20: Normal Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 ...
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Table 21: Reduced Output Drive Characteristics Characteristics are specified under best, worst, and nominal process variation/conditions Pull-Down Current (mA) Voltage Nominal Nominal (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 ...
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Commands Tables 22 and 23 provide a quick reference of available commands. Two additional Truth Tables—Table 24 on page 35 and Table 25 on page 36—provide current state/next state information. Table 22: Truth Table 1 – Commands CKE is HIGH ...
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Table 24: Truth Table 3 – Current State Bank n – Command to Bank n Notes: 1–6 apply to the entire table; Notes appear below Current State CS# RAS# CAS# Any Idle L L ...
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Accessing mode register: Starts with registration of an LMR command and ends when • Precharging all: Starts with registration of a PRECHARGE ALL command and ends when 6. All states and sequences not shown are illegal or reserved. 7. ...
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Exceptions are covered in the notes below. 3. Current state definitions: • Idle: The bank has been precharged, and • Row active: A row in the ...
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Table 27: Truth Table 5 – CKE Notes 1–6 apply to the entire table; Notes appear below CKE CKE Current State n Power-down Self refresh L H Power-down Self refresh H L All banks idle Bank(s) active ...
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ACTIVE (ACT) The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access, like a read or a write, as shown in Figure 15. The value on the BA0, BA1 inputs selects ...
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READ The READ command is used to initiate a burst read access to an active row, as shown in Figure 16 on page 40. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs ...
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WRITE The WRITE command is used to initiate a burst write access to an active row as shown in Figure 17. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai and configuration, ...
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PRECHARGE (PRE) The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks as shown in Figure 18. The value on the BA0, BA1 inputs selects the bank, and the ...
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Operations INITIALIZATION Prior to normal operation, DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures, other than those specified, may result in undefined operation. To ensure device operation, the DRAM must be initialized as described ...
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Figure 19: INITIALIZATION Flow Diagram Step PDF: 09005aef80a2f898/Source: 09005aef82a95a3a DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B ...
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Figure 20: INITIALIZATION Timing Diagram ( ( ) ) VTD REF ) ) ( ( CK ...
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... A8, which is self- clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation ...
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Burst Length (BL) Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable for both READ and WRITE bursts, as shown in Figure 21 on page 46. The burst length determines the maximum ...
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CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set (-5B only) ...
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Table 29: CAS Latency Speed 75 ≤ f ≤ 133 -5B 75 ≤ f ≤ 133 -6T 75 ≤ f ≤ 100 -75 Operating Mode The normal operating mode is selected by issuing an LMR command with bits A7–An each ...
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Figure 23: Extended Mode Register Definition Notes the most significant row address bit from Table 2 on page 2. 2. The reduced drive strength option is available only on the ...
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Figure 24: Example: Meeting T0 T1 CK# CK ACT Command NOP Row Address Bank x BA0, BA1 READ During the READ command, the value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, ...
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Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 29 on page 57. The BURST TERMINATE latency is equal to the CL, that is, the BURST TERMINATE command should be issued x ...
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Figure 25: READ Burst CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ Notes data-out from column Three subsequent elements of ...
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Figure 26: Consecutive READ Bursts CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ Notes ( data-out from column n (or column b ...
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Figure 27: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes: 1. ...
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Figure 28: Random READ Accesses CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ Notes ( data-out from column n (or column ...
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Figure 29: Terminating a READ Burst CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ Notes: 1. Page remains open data-out from column ...
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Figure 30: READ-to-WRITE CK# CK Command READ Bank, Address Col n DQS DQ DM CK# CK Command READ Bank, Address Col n DQS DQ DM CK# CK READ Command Bank a, Address Col n DQS DQ DM Notes: 1. Page ...
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Figure 31: READ-to-PRECHARGE CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ CK# CK Command Address DQS DQ Notes: 1. Provided precharge to be performed at x number of clock cycles after the READ command, where x ...
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Figure 32: Bank READ – Without Auto Precharge CKE Command NOP ACT t IS Row Address A10 Row t IS BA0, BA1 Bank ...
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Figure 33: x4, x8 Data Output Timing – DQ (first data no longer valid) DQ (first data no longer valid) All DQ and DQS collectively t Notes the lesser DQSQ is derived at each ...
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Figure 34: x16 Data Output Timing – LDQS 3 DQ (last data valid) DQ (first data no longer valid) DQ (last data valid) DQ (first data no longer valid) DQ0–DQ7 and LDQS collectively UDQS DQ (last data valid) DQ (first ...
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... WRITE burst (after selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location ...
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Figure 36 on page 65 shows the nominal case and the extremes of t DQSS for Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and ...
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Figure 36: WRITE Burst Command Address t DQSS (NOM) t DQSS (MIN) t DQSS (MAX) Notes data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following ...
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Figure 37: Consecutive WRITE-to-WRITE CK# CK Command Address t DQSS (NOM) DQS DQ DM Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order ...
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Figure 38: Nonconsecutive WRITE-to-WRITE CK# Command Address t DQSS (NOM) DQS Notes ( data-in from column b (or column n). 2. Three subsequent elements of data-in are applied in the programmed order following DI b. ...
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Figure 40: WRITE-to-READ – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 41: WRITE-to-READ – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS ...
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Figure 43: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS DQ DM Notes: ...
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Figure 44: WRITE-to-PRECHARGE – Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS DQS DQ DM Notes: ...
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Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) ...
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Figure 46: Bank WRITE – Without Auto Precharge CKE NOP 1 Command ACT Row Address A10 Row BA0, ...
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Figure 47: WRITE – DM Operation CKE ACT NOP Command Row Address A10 Row BA0, BA1 Bank ...
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Figure 48: Data Input Timing CK# CK DQS DQ DM Notes: 1. WRITE command issued at T0 DSH (MIN) generally occurs during t 3. DSS (MIN) generally occurs during 4. For x16, LDQS controls the lower byte and ...
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Figure 49: Bank READ – with Auto Precharge CKE ACT NOP Command Row Address A10 Row IS IH BA0, BA1 Bank ...
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Figure 50: Bank WRITE – with Auto Precharge CKE Command NOP ACT Row Address A10 Row BA0, ...
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Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends Figure 51: Auto Refresh Mode ...
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NOPs for 200 additional clock cycles before applying a READ. Any command other than a READ can be performed reset. NOP or DESELECT commands must be issued during the Figure 52: Self Refresh Mode T1 ...
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Power-down (CKE Not Active) Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command, until completion of the access. Thus a clock suspend ...
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Figure 53: Power-Down Mode Command Address Notes: 1. Once initialized this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is ...