MT46V64M16TG-6T:A TR Micron Technology Inc, MT46V64M16TG-6T:A TR Datasheet - Page 36

• Manufacturer Part Number: MT46V64M16TG-6T:A TR
• Description: IC DDR SDRAM 1GBIT 6NS 66TSOP
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M16TG-6T:A TR

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOP
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 275mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 25:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Current State
Any
Idle
Row activating, active, or
precharging
Read (auto precharge disabled)
Write (auto precharge
disabled)
Read (with auto-precharge)
Write (with auto-precharge)
Truth Table 4 – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table; Notes appear on page 36
Notes:
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted (that is, the current state
valid state for precharging.
bank.
precharge enabled and READs or WRITEs with auto precharge disabled.
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
after
is for bank n, and the commands shown are those allowed to be issued to bank m, assuming
• Accessing mode register: Starts with registration of an LMR command and ends when
• Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
CS#
t
state.
t
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
MRD has been met. Once
RP is met. Once
t
XSNR has been met (if the previous state was self refresh).
RAS# CAS# WE# Command/Action
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
t
RP is met, all banks will be in the idle state.
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
n-1
36
t
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
MRD is met, the DDR SDRAM will be in the all banks idle
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
1Gb: x4, x8, x16 DDR SDRAM
is HIGH (see Table 27 on page 38) and
©2003 Micron Technology, Inc. All rights reserved.
Commands
Notes
7, 9
7, 8
7, 9
7
7
7
7
7
7
7