IDT70T3339S133BC IDT, Integrated Device Technology Inc, IDT70T3339S133BC Datasheet - Page 20

• Manufacturer Part Number: IDT70T3339S133BC
• Description: IC SRAM 9MBIT 133MHZ 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70T3339S133BC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70T3339S133BC

Collision Detection Timing
Truth Table IV — Collision Detection Flag
NOTES:
1. CE
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3t
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
NOTES:
1. CE
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Waveform of Collision Timing
Both Ports Writing with Left Port Clock Leading
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
CLK
↑
↑
↑
↑
0
Cycle Time
0 =
L
= V
ADDRESS
7.5ns
V
ADDRESS
5ns
6ns
IL
IL
, CE
and CE
R/W
COL
H
H
L
L
CLK
COL
1
CLK
L
= V
(1)
R
1 =
L
(4)
R
(4)
R
L
L
IH
.
V
IH
Left Port
CE
. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
L
L
L
L
L
Region 1 (ns)
(1)
t
SA
0 - 2.8
0 - 3.8
0 - 5.3
A
0
t
SA
A
t
HA
18L
MATCH
MATCH
MATCH
MATCH
A
-A
0
t
t
CYC
OFS
HA
0L
(1)
(2)
2
t
OFS
+ t
COLS
(ns)
COL
A
after Address match.
H
H
L
L
1
Region 2 (ns)
L
2.81 - 4.6
3.81 - 5.6
5.31 - 7.1
A
(3,4)
1
CLK
↑
↑
↑
↑
5652 tbl 13
(1,2)
R
(2)
A
2
R/W
A
H
H
2
L
L
6.42
t
OFS
R
20
(1)
t
COLS
NOTES:
1. Region 1
2. Region 2
3. All the production units are tested to midpoint of each region.
4. These ranges are based on characterization of a typical device.
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
Right Port
CE
L
L
L
L
A
R
3
(1)
A
t
COLS
3
t
COLR
A
18R
MATCH
MATCH
MATCH
MATCH
Industrial and Commercial Temperature Ranges
-A
0R
(2)
(3)
t
COLR
COL
H
H
L
L
R
Both ports reading. Not a valid collision.
No flag output on either port.
Left port reading, Right port writing.
Right port reading, Left port writing.
Both ports writing. Valid collision. Flag
output on both ports.
Valid collision, flag output on Left port.
Valid collision, flag output on Right port.
5652 drw 20
Function
5652 tbl 14