IDT70T3339S133BC IDT, Integrated Device Technology Inc, IDT70T3339S133BC Datasheet - Page 22

• Manufacturer Part Number: IDT70T3339S133BC
• Description: IC SRAM 9MBIT 133MHZ 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70T3339S133BC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 9M (512K x 18)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70T3339S133BC

Functional Description
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3339/19/99s for depth
expansion configurations. Two cycles are required with CE
CE
Interrupts
flag (INT
7FFFE (HEX), where a write is defined as CE
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when CE
right port interrupt flag (INT
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (INT
or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399). The
message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T3319
and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and
1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table III for the interrupt
operation.
Collision Detection
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no data
is corrupted, lost, or incorrectly output, so no collision flag is output on either
port. (b) One port writing, the other port reading - the end result of the write
will still be valid. However, the reading port might capture data that is in
a state of transition and hence the reading port’s collision flag is output. (c)
Both ports writing - there is a risk that the two ports will interfere with each
other, and the data stored in memory will not be a valid write from either
port (it may essentially be a random combination of the two). Therefore,
the collision flag is output on both ports. Please refer to Truth Table IV for
all of the above cases.
of the affected port following the collision, and remains low for one cycle.
Please refer to Collision Detection Timing table on page 20. During that
next cycle, the internal arbitration is engaged in resetting the alert flag (this
avoids a specific requirement on the part of the user to reset the alert flag).
If two collisions occur on subsequent clock cycles, the second collision may
not generate the appropriate alert flag. A third collision will generate the
box or message center) is assigned to each port. The left port interrupt
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
1
The IDT70T3339/19/99 provides a true synchronous Dual-Port Static
An asynchronous output enable is provided to ease asyn-
A HIGH on CE
If the user chooses the interrupt function, a memory location (mail
HIGH to re-activate the outputs.
The alert flag (COL
Collision is defined as an overlap in access between the two ports
R
L
) is asserted when the right port writes to memory location
), the right port must read the memory location 7FFFF (3FFFF
0
or a LOW on CE
X
) is asserted on the 2nd or 3rd rising clock edge
L
1
= V
R
for one clock cycle will power down
) is asserted when the left
IL
and R/WL = V
R
= R/W
IH
R
. Likewise, the
= V
0
LOW and
IL
per the
6.42
22
alert flag as appropriate. In the event that a user initiates a burst access
on both ports with the same starting address on both ports and one or both
ports writing during each access (i.e., imposes a long string of collisions
on contiguous clock cycles), the alert flag will be asserted and cleared
every other cycle. Please refer to the Collision Detection Timing waveform
on page 20.
advance in functionality over current sync multi-ports, which have no such
capability. In addition to this functionality the IDT70T3339/19/99 sustains
the key features of bandwidth and flexibility. The collision detection function
is very useful in the case of bursting data, or a string of accesses made to
sequential addresses, in that it indicates a problem within the burst, giving
the user the option of either repeating the burst or continuing to watch the
alert flag to see whether the number of collisions increases above an
acceptable threshold value. Offering this function on chip also allows users
to reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s. This reduces board space and design complexity, and gives the
user more flexibility in developing a solution.
Sleep Mode
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulled low. When ZZ is pulled high, the port will enter sleep mode where
it will meet lowest possible power conditions. The sleep mode timing
diagram shows the modes of operation: Normal Operation, No Read/Write
Allowed and Sleep Mode.
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = V
must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/Wx = V
enable must be valid for one full cycle before a read will result in the output
of valid data.
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (I
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
Collision detection on the IDT70T3339/19/99 represents a significant
The IDT70T3339/19/99 is equipped with an optional sleep or low
For normal operation all inputs must meet setup and hold times prior
During sleep mode the RAM automatically deselects itself. The RAM
IH
) and three cycles after de-asserting ZZ (ZZx = V
Industrial and Commercial Temperature Ranges
IH
)when chip enable is asserted, and the chip
ZZ
). All outputs will remain in
IL
), the device