MT48H32M16LFCJ-75 L IT:A TR Micron Technology Inc, MT48H32M16LFCJ-75 L IT:A TR Datasheet - Page 21

• Manufacturer Part Number: MT48H32M16LFCJ-75 L IT:A TR
• Description: IC SDRAM 512MBIT 133MHZ 54VBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H32M16LFCJ-75 L IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1331-2

Auto Precharge
BURST TERMINATE
AUTO REFRESH
SELF REFRESH
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is non persistent in that it is either enabled or disabled for each indi-
vidual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (
issued at the earliest possible time, as described for each burst type in "Burst Type" on
page 13.
The BURST TERMINATE command is used to truncate fixed-length bursts. The most
recently registered READ or WRITE command prior to the BURST TERMINATE
command will be truncated, as shown in "Operations" on page 22.
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is non
persistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum
PRECHARGE command, as shown in "Operations" on page 22.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires
8,192 AUTO REFRESH cycles every 64ms (
REFRESH command every 7.8125µs will meet the refresh requirement and ensure that
each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a
burst at the minimum cycle rate (
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO
REFRESH command, except CKE is disabled (LOW). Once the SELF REFRESH command
is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking,
causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock ball) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for
required for the completion of any internal refresh in progress.
t
RP) is completed. This is determined as if an explicit PRECHARGE command was
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
21
t
RFC), once every 64ms.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF). Providing a distributed AUTO
t
RAS and may remain in self refresh mode
t
RP has been met after the
t
XSR because time is
©2005 Micron Technology, Inc. All rights reserved.
Commands