MT48H32M16LFCJ-75 L IT:A TR Micron Technology Inc, MT48H32M16LFCJ-75 L IT:A TR Datasheet - Page 42

• Manufacturer Part Number: MT48H32M16LFCJ-75 L IT:A TR
• Description: IC SDRAM 512MBIT 133MHZ 54VBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H32M16LFCJ-75 L IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1331-2

Table 7:
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
(auto precharge
(auto precharge
Current State
Row active
disabled)
disabled)
Write
Read
Any
Idle
Truth Table – Current State Bank n, Command to Bank n
Notes: 1–6; notes appear below table
Notes:
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
RAS# CAS#
after
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
MAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 7, and according to Table 8 on page 44.
Idle:
Row active:
Read:
Write:
Precharging:
Row activating:
Read w/auto-
precharge enabled:
Write w/auto-
precharge enabled:
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
t
XSR has been met (if the previous state was self refresh).
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
WE#
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
The bank has been precharged, and
A row in the bank has been activated, and
bursts/accesses and no register accesses are in progress.
not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
A READ burst has been initiated, with auto precharge disabled, and has
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Starts with registration of a PRECHARGE command and ends when
t
Starts with registration of an ACTIVE command and ends when
is met. Once
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
RP is met. Once
n-1
42
was HIGH and CKE
t
RCD is met, the bank will be in the row active state.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, the bank will be in the idle state.
t
t
RP has been met. Once
RP has been met. Once
n
is HIGH (see Table 6 on page 41) and
t
RP has been met.
t
RCD has been met. No data
©2005 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank
RP is met, the bank
Truth Tables
Notes
10
10
11
10
11
7
7
8
9
9
9
9
9
9
t
RCD