MT48H32M16LFCJ-75 L IT:A TR Micron Technology Inc, MT48H32M16LFCJ-75 L IT:A TR Datasheet - Page 23

• Manufacturer Part Number: MT48H32M16LFCJ-75 L IT:A TR
• Description: IC SDRAM 512MBIT 133MHZ 54VBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H32M16LFCJ-75 L IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1331-2

Figure 9:
Figure 10:
READs
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
Activating a Specific Row in a Specific Bank
Example: Meeting
BA0, BA1
READ bursts are initiated with a READ command, as shown in Figure 11.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 12 on page 25 shows general
timing for each possible CL setting.
COMMAND
A0–A12
RAS#
CAS#
WE#
CKE
CLK
CS#
CLK
t
RCD (MIN) When 2 <
HIGH
ACTIVE
T0
t CK
ADDRESS
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
ADDRESS
BANK
ROW
t
NOP
RCD (MIN)
T1
23
DON´T CARE
t CK
t
RCD (MIN)/
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
t CK
t
CK < 3
READ or
DON’T CARE
WRITE
T3
©2005 Micron Technology, Inc. All rights reserved.
Operations