MT41J128M8HX-187E:D TR Micron Technology Inc, MT41J128M8HX-187E:D TR Datasheet - Page 130

• Manufacturer Part Number: MT41J128M8HX-187E:D TR
• Description: IC DDR3 SDRAM 1GBIT 78FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT41J128M8HX-187E:D TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1377-1

PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Data from any READ burst must be completed before a subsequent WRITE burst is
allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in
Figure 73 on page 132 (BC4 is shown in Figure 74 on page 133). To ensure the read data is
completed before the write data is on the bus, the minimum READ-to-WRITE timing is
RL +
A READ burst may be followed by a PRECHARGE command to the same bank provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command
spacing to the same bank is four clocks and must also satisfy a minimum analog time
from the READ command. This time is called
AL cycles later than the READ command. Examples for BL8 are shown in Figure 75 on
page 133 and BC4 in Figure 76 on page 134. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until
PRECHARGE command followed by another PRECHARGE command to the same bank
is allowed. However, the precharge period will be determined by the last PRECHARGE
command issued to the bank.
If A10 is HIGH when a READ command is issued, the READ with auto precharge function
is engaged. The DRAM starts an auto precharge operation on the rising edge which is AL
+
Figure 78 on page 134). If
auto precharge operation will be delayed until
not satisfied at the edge, the starting point of the auto precharge operation will be
delayed until
t
rising clock edge after this event). The time from READ with auto precharge to the next
ACTIVATE command to the same bank is AL + (
up to the next integer. In any event, internal precharge does not start earlier than four
clocks after the last 8n-bit prefetch.
RTP,
t
RTP cycles after the READ command. DRAM support a
t
t
CCD - WL + 2
RP starts at the point at which the internal precharge happens (not at the next
t
RTP (MIN) is satisfied. In case the internal precharge is pushed out by
t
CK.
t
RAS (MIN) is not satisfied at the edge, the starting point of the
130
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t
RTP (READ-to-PRECHARGE).
t
t
RAS (MIN) is satisfied. If
RTP +
1Gb: x4, x8, x16 DDR3 SDRAM
t
RP)*, where “*” means rounded
t
RAS lockout feature (see
©2006 Micron Technology, Inc. All rights reserved.
t
RP is met. The
t
RTP (MIN) is
Operations
t
RTP starts