MT41J512M8THU-15E:A Micron Technology Inc, MT41J512M8THU-15E:A Datasheet - Page 139

• Manufacturer Part Number: MT41J512M8THU-15E:A
• Description: IC DDR3 SDRAM 4GBIT 82FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT41J512M8THU-15E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 4G (512M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 77: Data Strobe Timing – READs
Figure 78: Method for Calculating
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
early strobe
DQS, DQS#
DQS, DQS#
late strobe
CK#
CK
t HZ (DQS), t HZ (DQ)
t LZ (DQS) MIN
t HZ (DQS), t HZ (DQ) end point = 2 × T1 - T2
Notes:
T0
t LZ (DQS) MAX
t RPRE
t
parameters are referenced to a specific voltage level which specifies when the device
output is no longer driving
t
driving
signal at two different voltages. The actual voltage measurement points are not critical
as long as the calculation is consistent. The parameters
and
1. Within a burst, the rising strobe edge is not necessarily fixed at
2. The DQS high pulse width is defined by
3. The minimum pulse width of the READ preamble is defined by
HZ and
LZ (DQ). Figure 78 shows a method to calculate the point when the device is no longer
t DQSCK (MIN)
(MAX). Instead, the rising strobe edge can vary between
t
case) and
case); however, they tend to track one another.
pulse width of the READ postamble is defined by
QSL. Likewise,
t
HZ (DQ) are defined as single-ended.
t RPRE
Bit 0
RL measured
to this point
t
HZ (DQS) and
t
LZ transitions occur in the same access time as valid data transitions. These
T1
T1
t QSH
t DQSCK (MAX)
t
LZ (DQS) MAX and
T2
Bit 0
t
Bit 1
LZ and
t QSH
t
t DQSCK (MIN)
LZ (DQS) MIN and
t QSL
Bit 1
V
V
V
V
Bit 2
OH
OH
OL
OL
t
t
HZ (DQ) or begins driving
HZ
t QSL
+ 2xmV
+ xmV
- xmV
- 2xmV
T2
t QSH
t DQSCK (MAX)
t
HZ (DQS) and
Bit 2
139
Bit 3
t
HZ (DQS) MAX are not tied to
t QSH
t DQSCK (MIN)
t QSL
t
HZ (DQS) MIN are not tied to
Bit 4
Bit 3
V
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V
V
t QSL
TT
V
t
TT
T3
QSH, and the DQS low pulse width is defined by
TT
TT
+ 2xmV
t DQSCK (MAX)
- 2xmV
t
+ xmV
t LZ (DQS), t LZ (DQ) begin point = 2 × T1 - T2
HZ (DQ) or begins driving
- xmV
Bit 4
Bit 5
t DQSCK (MIN)
2Gb: x4, x8, x16 DDR3 SDRAM
t
RPST (MIN).
t
LZ (DQS),
Bit 5
Bit 6
T1
t
T4
t
T2
LZ (DQS),
DQSCK (MIN) and
t DQSCK (MAX)
Bit 6
t
Bit 7
DQSCK (MAX) (late strobe
t
LZ (DQ) by measuring the
t
t
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RPRE (MIN). The minimum
t
t LZ (DQS), t LZ (DQ)
DQSCK (MIN) or
t HZ (DQS) MIN
t RPST
DQSCK (MIN) (early strobe
t
LZ (DQ),
Bit 7
t
t RPST
LZ (DQS),
T5
t HZ (DQS) MAX
t
Operations
DQSCK (MAX).
t
HZ (DQS),
t
DQSCK
T6