MT41J512M8THU-15E:A Micron Technology Inc, MT41J512M8THU-15E:A Datasheet - Page 23

• Manufacturer Part Number: MT41J512M8THU-15E:A
• Description: IC DDR3 SDRAM 4GBIT 82FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT41J512M8THU-15E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 4G (512M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D2.fm - Rev G 2/09 EN
A9, B3, E1, G8, J2, J8,
J1, J9, L1, L9, M7, T7
Ball Assignments
M1, M9, P1, P9, T1,
B2, D9, G7, K2, K8,
A1, A8, C1, C9, D2,
B1, B9, D1, D8, E2,
N1, N9, R1, R9
E9, F1, H2, H9
E8, F9, G1, G9
F8, H3, H8,
E3, F7, F2,
A7, A2,
D7, C3,
G2, H7
C8, C2,
B8, A3
F3, G3
C7, B7
M8
D3
H1
T2
T9
L8
96-Ball FBGA – x16 Ball Descriptions (continued)
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
UDQS, UDQS#
DQ10, DQ11,
DQ12, DQ13,
LDQS, LDQS#
DQ14, DQ15
DQ8, DQ9,
DQ6, DQ7
Symbol
V
RESET#
V
V
UDM
REF
V
REF
V
V
ZQ
NC
DD
SS
DD
SS
DQ
CA
Q
Q
Reference External reference ball for output drive calibration: This ball is
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Type
I/O
I/O
I/O
I/O
–
Description
Reset: RESET# is an active LOW CMOS input referenced to V
RESET# input receiver is a CMOS input defined as a rail-to-rail signal
with DC HIGH ≥ 0.8 × V
assertion and desertion are asynchronous.
Input data mask: UDM is an upper-byte, input mask signal for
write data. Upper-byte input data is masked when UDM is sampled
HIGH along with that input data during a WRITE access. Although
the UDM ball is input-only, the UDM loading is designed to match
that of the DQ and DQS balls. UDM is referenced to V
Data input/output: Lower byte of bidirectional data bus for the x16
configuration. DQ[7:0] are referenced to V
Data input/output: Upper byte of bidirectional data bus for the x16
configuration. DQ[15:8] are referenced to V
Lower byte data strobe: Output with read data. Edge-aligned
with read data. Input with write data. Center-aligned to write data.
Upper byte data strobe: Output with read data. Edge-aligned with
read data. Input with write data. DQS is center-aligned to write data.
Power supply: 1.5V ±0.075V.
DQ power supply: 1.5V ±0.075V. Isolated on the device for
improved noise immunity.
Reference voltage for control, command, and address: V
must be maintained at all times (including self refresh) for proper
device operation.
Reference voltage for data: V
times (excluding self refresh) for proper device operation.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
tied to an external 240Ω resistor (RZQ), which is tied to V
No connect: These balls should be left unconnected (the ball has no
connection to the DRAM or to other balls).
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
DD
and DC LOW ≤ 0.2 × V
2Gb: x4, x8, x16 DDR3 SDRAM
REF
DQ must be maintained at all
©2006 Micron Technology, Inc. All rights reserved.
REF
REF
DQ.
DQ.
DD
Q. RESET#
REF
DQ.
SS
Q.
SS
. The
REF
CA