MT41J512M8THU-15E:A Micron Technology Inc, MT41J512M8THU-15E:A Datasheet - Page 31
MT41J512M8THU-15E:A
Manufacturer Part Number
MT41J512M8THU-15E:A
Description
IC DDR3 SDRAM 4GBIT 82FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT41J256M8JE-187EA.pdf
(181 pages)
Specifications of MT41J512M8THU-15E:A
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
4G (512M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
82-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 11:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D2.fm - Rev G 2/09 EN
0
1
2
3
4
5
6
7
I
DD
1 Measurement Loop
nRC + nRCD
nRC + nRAS
Notes:
10 × nRC
12 × nRC
14 × nRC
nRC + 1
nRC + 2
nRC + 3
nRC + 4
2 × nRC
4 × nRC
6 × nRC
8 × nRC
nRCD
nRAS
nRC
0
1
2
3
4
1. DQs, DQS, DQS# are mid-level unless driven as required by the READ (RD) command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. Only selected bank (single) active.
ACT
ACT
PRE
PRE
RD
RD
D#
D#
D#
D#
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed
D
D
D
D
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed
Electrical Specifications – I
Repeat cycle nRC + 1 through nRC + 4 until 2 × nRC - 1, truncate if needed
Repeat cycles 1 through 4 until nRCD - 1, truncate if needed
Repeat cycles 1 through 4 until nRAS - 1, truncate if needed
0
1
1
1
1
0
0
0
1
1
1
1
0
0
Repeat cycles 1 through 4 until nRC - 1, truncate if needed
0
0
0
1
1
1
0
0
0
0
1
1
1
0
1
0
0
1
1
0
1
1
0
0
1
1
0
1
Repeat sub-loop 0, use BA[2:0] = 1
Repeat sub-loop 0, use BA[2:0] = 2
Repeat sub-loop 0, use BA[2:0] = 3
Repeat sub-loop 0, use BA[2:0] = 4
Repeat sub-loop 0, use BA[2:0] = 5
Repeat sub-loop 0, use BA[2:0] = 6
Repeat sub-loop 0, use BA[2:0] = 7
31
1
0
0
1
1
1
0
1
0
0
1
1
1
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DD
2Gb: x4, x8, x16 DDR3 SDRAM
Specifications and Conditions
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
©2006 Micron Technology, Inc. All rights reserved.
0
0
0
0
0
0
0
F
F
F
F
F
F
F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000
00110011
–
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