CY7C138-25JC Cypress Semiconductor Corp, CY7C138-25JC Datasheet - Page 10

• Manufacturer Part Number: CY7C138-25JC
• Description: IC SRAM 32KBIT 25NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C138-25JC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Density: 32Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 12b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Word Size: 8b
• Number Of Words: 4K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1445

Switching Waveforms
Notes
Document #: 38-06037 Rev. *E
27. I/O
28. Semaphores are reset (available to both ports) at cycle start.
29. If t
SPS
0R
ADDRESS
ADDRESS
= I/O
DATA
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
BUSY
DATA IN
R/W
BUSY
0L
R/W
OUTL
= LOW (request semaphore); CE
R
L
R
R
L
Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH)
(continued)
t
PS
Figure 11. Write Timing with Busy Input (M/S=LOW)
R
= CE
t
WB
L
= HIGH
t
BLA
MATCH
MATCH
t
PWE
t
WC
t
PWE
t
WH
t
WDD
t
VALID
SD
t
DDD
[21]
t
HD
CY7C138, CY7C139
t
BHA
t
BDD
VALID
Page 10 of 17
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