CY7C138-25JC Cypress Semiconductor Corp, CY7C138-25JC Datasheet - Page 11

• Manufacturer Part Number: CY7C138-25JC
• Description: IC SRAM 32KBIT 25NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C138-25JC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Density: 32Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 12b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Word Size: 8b
• Number Of Words: 4K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1445

Switching Waveforms
Note
Document #: 38-06037 Rev. *E
30. If t
CE
CE
Right Address Valid First:
Left Address Valid First:
ADDRESS
ADDRESS
PS
R
L
ADDRESS
ADDRESS
ADDRESS
ADDRESS
Valid First:
Valid First:
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
BUSY
BUSY
BUSY
BUSY
CE
CE
CE
CE
L,R
L,R
R
R
R
R
L
L
L
R
R
L
L
L
Figure 13. Busy Timing Diagram No. 2 (Address Arbitration)
(continued)
Figure 12. Busy Timing Diagram No. 1 (CE Arbitration)
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
t
t
RC
RC
or t
or t
t
t
PS
PS
WC
WC
t
t
BLA
BLA
ADDRESS MATCH
ADDRESS MATCH
t
t
BLC
BLC
ADDRESS MISMATCH
ADDRESS MISMATCH
t
t
BHA
BHA
t
t
BHC
BHC
[30]
[30]
CY7C138, CY7C139
Page 11 of 17
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