CY7C138-25JC Cypress Semiconductor Corp, CY7C138-25JC Datasheet - Page 13

• Manufacturer Part Number: CY7C138-25JC
• Description: IC SRAM 32KBIT 25NS 68PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C138-25JC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Density: 32Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 12b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Word Size: 8b
• Number Of Words: 4K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1445

Architecture
The CY7C138/9 consists of an array of 4K words of 8/9 bits each
of dual-port RAM cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access
for reads or writes to any location in memory. To handle simulta-
neous writes and reads to the same location, a BUSY pin is
provided on each port. Two interrupt (INT) pins can be used for
port–to–port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S pin,
the CY7C138/9 can function as a master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). The CY7C138/9
has an automatic power down feature controlled by CE. Each
port is provided with its own output enable control (OE), which
enables data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W in order to guarantee a valid write. A write operation is
controlled by either the OE pin (see Write Cycle No. 1 waveform)
or the R/W pin (see Write Cycle No. 2 waveform). Data can be
written to the device t
after the falling edge of R/W. Required inputs for non-contention
operations are summarized in
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
asserted. If the user of the CY7C138/9 wishes to access a
semaphore flag, then the SEM pin must be asserted instead of
the CE pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location FFF, the right port’s
interrupt flag (INT
reads that same location. Setting the left port’s interrupt flag
(INT
This flag is cleared when the left port reads location FFE. The
message at FFF or FFE is user-defined. See
requirements for INT. INT
do not require pull-up resistors to operate. BUSY
in master mode are push-pull outputs and do not require pull-up
resistors to operate.
Busy
The CY7C138/9 provides on-chip arbitration to alleviate simulta-
neous memory location access (contention). If both ports’ CEs
are asserted and an address match occurs within t
other the Busy logic determines which port has access. If t
violated, one port definitely gains permission to the location, but
it is not guaranteed which one. BUSY will be asserted t
an address match or t
Document #: 38-06037 Rev. *E
L
) is accomplished when the right port writes to location FFE.
R
) is set. This flag is cleared when the right port
HZOE
BLC
R
after CE is taken LOW.
after the OE is deasserted or t
and INT
ACE
Table
after CE or t
L
3.
are push-pull outputs and
SD
before the rising edge
Table 4
DOE
L
and BUSY
after OE is
PS
DDD
BLA
for input
of each
HZWE
PS
after
after
is
R
Master/Slave
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This enables
the device to interface to a master device with no external
components.Writing of slave devices must be delayed until after
the BUSY input has settled. Otherwise, the slave chip may begin
a write cycle during a contention situation.When presented as a
HIGH input, the M/S pin allows the device to be used as a master
and therefore the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Semaphore Operation
The CY7C138/9 provides eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be deasserted
for t
semaphore value is available t
of the semaphore write. If the left port was successful (reads a
zero), it assumes control over the shared resource, otherwise
(reads a one) it assumes the right port has control and continues
to poll the semaphore.When the right side has relinquished
control of the semaphore (by writing a one), the left side
succeeds in gaining control of the a semaphore.If the left side no
longer requires the semaphore, a 1 is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an unused semaphore, a one will appear
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to 1 for
both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port immediately owns the semaphore after the left port
releases it.
When reading a semaphore, all eight or nine data lines output
the semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within t
obtained by one side or the other, but there is no guarantee which
side controls the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program at power up. All semaphores on both
sides should have a 1 written into them at initialization from both
sides to assure that they are free when needed.
SOP
before attempting to read the semaphore. The
Table 5
SPS
shows sample semaphore operations.
of each other, the semaphore is definitely
SWRD
CY7C138, CY7C139
+ t
DOE
0
is used. If a zero is
after the rising edge
0–2
represents the
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