DSM2180F3V-15K6 STMicroelectronics, DSM2180F3V-15K6 Datasheet - Page 8

• Manufacturer Part Number: DSM2180F3V-15K6
• Description: IC FLASH 1MBIT 150NS 52PLCC
• Manufacturer: STMicroelectronics

Specifications of DSM2180F3V-15K6

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1336-5

DSM2180F3V
Figure 5. Block Diagram
Programmable Logic (PLDs)
The DSM family contains two PLDS that may op-
tionally run in Turbo or Non-Turbo mode. PLDs op-
erate faster (less propagation delay) while in
Turbo mode but consume more power than Non-
Turbo mode. Non-Turbo mode allows the PLDs to
automatically go to standby when no inputs are
change to conserve power. The Turbo mode set-
ting is controlled at runtime by DSP software.
Decode PLD (DPLD). This is programmable log-
ic used to select one of the eight individual Flash
memory segments or the group of control registers
within the DSM device. The DPLD can also option-
ally drive external chip select signals on Port D
pins. DPLD input signals include: DSP address
and control signals, Page Register outputs, DSM
Port Pins, CPLD logic feedback.
Complex PLD (CPLD). This programmable logic
is used to create both combinatorial and sequen-
tial general purpose logic. The CPLD contains 16
Output Macrocells (OMCs) and 16 Input Macro-
cells (IMCs). PSD Macrocell registers are unique
in that that have direct connection to the DSP data
bus allowing them to be loaded and read directly
by the DSP at runtime. This direct access is good
8/63
CONTROL
ADDR
DSP
DSP
CNTL0
CNTL1
CNTL2
PD0
PD1
PD2
RST\
AD10
AD11
AD12
AD13
AD14
AD15
SECURITY
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
PC2
PC7
LOCK
PIN FEEDBACK
NODE FEEDBACK
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP
CHIP SELECTS
COMPLEX PLD
DECODE PLD
EXTERNAL
PAGE REG
(DPLD)
(CPLD)
ARRAY
AND
16 OUTPUT MICRO<>CELLS
EXTERNAL CHIP SELECTS, ESC0-2
CSIOP
B
C
3 OPTIONAL OUTPUTS TO PORT D
FS0-7
A
B
B
C
B
C C
A
B
B
C
MICRO<>CELLS
B
A
B
B
C
16 INPUT
B
C
fs0
B
C
A
B
fs1
fs2
POWER MANAGEMENT
8 SEGMENTS, 16 KB
fs3
CSIOP REGISTER FILE
fs4
128 KBytes TOTAL
fs5
C
RUNTIME CONTROL
B
A
B
B
C
fs6
for making small peripheral devices (shifters,
counters, state machines, etc.) that are accessed
directly by the DSP with little overhead. DPLD in-
puts include DSP address and control signals,
Page Register outputs, DSM Port Pins, and CPLD
feedback.
OMCs: The general structure of the CPLD is simi-
lar in nature to a 22V10 PLD device with the famil-
iar sum-of-products (AND-OR) construct. True
and compliment versions of 64 input signals are
available to a large AND array. AND array outputs
feed into a multiple product-term OR gate within
each OMC (up to 10 product-terms for each
OMC). Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flip-
flop within in each OMC to realize sequential logic.
OMCs can be used as a buried nodes with feed-
back to the AND array or OMC output can be rout-
ed to pins on Port B or PortC.
IMCs: Inputs from pins on Port B or Port C are
routed to IMCs for conditioning (clocking or latch-
ing) as they enter the chip, which is good for sam-
pling and debouncing inputs. Alternatively, IMCs
can pass Port input signals directly to PLD inputs
FLASH MEMORY
fs7
B
C
C
A
B
B
A
B
B
C
B
C
A
B
B
C
B
C
TO ALL AREAS
JTAG-ISP
OF CHIP
CATOR
ALLO-
DSP SYSTEM
DSM2180F3
MEMORY
I/O PORT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
I/O PORT
PC0
PC1
PC3
PC4
PC5
PC6
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
DATA
DSP
AI04911