NAND512W3A2CN6E NUMONYX, NAND512W3A2CN6E Datasheet
NAND512W3A2CN6E
Specifications of NAND512W3A2CN6E
Available stocks
Related parts for NAND512W3A2CN6E
NAND512W3A2CN6E Summary of contents
Page 1
... Development tools – Error correction code models – Bad blocks management and wear leveling algorithms – Hardware simulation models Rev 5 NAND512R3A2C Not For New Design TSOP48 (N) FBGA VFBGA55 1.05 mm (ZD) VFBGA63 1.05 mm (ZA) Root part number NAND512R3A2C NAND512R4A2C NAND512W3A2C www.numonyx.com 1/55 1 ...
Page 2
... Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 Inputs/outputs (I/O0-I/O7 3.2 Inputs/outputs (I/O8-I/O15 3.3 Address Latch Enable (AL 3.4 Command Latch Enable (CL 3.5 Chip Enable ( 3.6 Read Enable ( 3.7 Write Enable ( 3.8 Write Protect (WP 3.9 Ready/Busy (RB 3.10 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
... Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7.1 6.7.2 6.7.3 6.7.4 6.8 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.6.1 7.6.2 8 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 34 9 Maximum ratings ...
Page 4
List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
... Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. VFBGA55 connections - x8 devices (top view through package Figure 5. VFBGA63 connections - x8 devices (top view through package Figure 6. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Pointer operations Figure 8. Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9. Read (A,B,C) operations Figure 10. ...
Page 6
... Serial number (unique identifier) option, which enables each device to be uniquely identified subject to an NDA and is, therefore, not described in the datasheet. For more details about these security features, contact your nearest Numonyx sales office. For information on how to order these devices refer to scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’ ...
Page 7
... NAND512-A2C Table 2. Product description Reference Part number Density NAND512R3A2C NAND512W3A2C 512 NAND512-A2C Mbits NAND512R4A2C Figure 1. Logic diagram Bus Page Block Memory Operating width size size array voltage 1.7 to 1.95 V 512+16 16K+512 x8 bytes bytes 32 pages x 2.7 to 3.6 V 4096 blocks 256+8 8K+256 x16 1 ...
Page 8
... Do not use Figure 2. Logic block diagram Address register/counter Command interface E logic WP R Command register 8/55 Function memory array P/E/R controller, high voltage generator Page buffer Y decoder I/O buffers & latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 NAND512-A2C Direction I/O I/O Input Input Input ...
Page 9
NAND512-A2C Figure 3. TSOP48 connections - x8 devices NAND flash (x8 ...
Page 10
Description Figure 4. VFBGA55 connections - x8 devices (top view through package 10/ ...
Page 11
NAND512-A2C Figure 5. VFBGA63 connections - x8 devices (top view through package ...
Page 12
... The memory array is made up of NAND structures where 16 cells are connected in series. The memory array is organized in blocks where each block contains 32 pages. The array is split into two areas, the main area and the spare area. The main area of the array is used to store data whereas the spare area is typically used to store error correction codes, software flags or bad block identification ...
Page 13
... Block Page 512 Bytes Page buffer, 512 bytes 512 bytes Block Page 8 bits 16 bytes 16 8 bits bytes Memory array organization x16 DEVICES Block = 32 pages Page = 264 words (256+8) Main area 16 bits 256 words 8 words Page buffer, 264 words 8 256 words words ...
Page 14
... When CL is High, the inputs are latched on the rising edge of Write Enable. 3.5 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and read circuitry. When Chip Enable is Low Chip Enable goes High (V remains selected and does not go into standby mode. ...
Page 15
... V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V (see Figure 36: Data operations during power-transitions ...
Page 16
Signal descriptions 3.11 V ground SS Ground the reference for the power supply. It must be connected to the system SS, ground. 16/55 NAND512-A2C ...
Page 17
... Table 4.4 Data output Data Output bus operations are used to read: the data in the memory array, the status register, the electronic signature and the serial number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low, and Command Latch Enable is Low. ...
Page 18
... Write protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up. ...
Page 19
NAND512-A2C Table 8. Address definition Address A25 A9 - A13 A14 - A25 A8 is set Low or High by the 00h or 01h command, A8 Bus operations Definition Column address Page address Address in ...
Page 20
Command set 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
Page 21
... The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device. In x16 devices the Read A command (00h) sets the pointer to area A (the whole of the main area) that is words 0 to 255 ...
Page 22
... Only Areas C can be programmed. Subsequent 50h commands can be omitted. 6.2 Read memory array Each operation to read the memory area starts with a pointer operation as shown in the Section 6.1: Pointer Read A, Read B or Read C commands four bus cycles (for 512-Mbit and 1-Gbit devices) or ...
Page 23
NAND512-A2C 6.2.2 Page read After the random read access the page data is transferred to the page buffer in a time of t (refer to Table 21 WHBH goes High. The data can then be read out sequentially (from selected ...
Page 24
Device operations Figure 10. Sequential row read operations (Read busy time) RB 00h/ I/O Address inputs 01h/ 50h Command code Figure 11. Sequential row read block diagrams Read A command, x8 devices Area B Area A (2nd half Page) (1st ...
Page 25
... NAND512-A2C 6.3 Page program The page program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. The maximum number of consecutive partial page program operations allowed in the same page is three ...
Page 26
... The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block ...
Page 27
... The Reset command is used to reset the command interface and status register. If the Reset command is issued during any operation, the operation will be aborted was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. ...
Page 28
... The error bit is used to identify if any errors have been detected by the P/E/R controller. The error bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to ‘0’ the operation has completed successfully. 6.7.4 SR5, SR4, SR3, SR2 and SR1 are reserved Table 11 ...
Page 29
NAND512-A2C 6.8 Read electronic signature The device contains a manufacturer code and device code. To read these codes two steps are required: 1. first use one bus write cycle to issue the Read Electronic Signature command (90h), followed by an ...
Page 30
... To help integrate a NAND memory into an application Numonyx can provide a full range of software solutions: file system, sector management, drivers, and code management. Contact the nearest Numonyx sales office or visit www.numonyx.com for more details. ...
Page 31
NAND512-A2C Table 13. NAND flash failure modes Operation Erase Program Read Figure 16. Bad block management flowchart Procedure Block Replacement Block Replacement START Block Address = Block 0 Increment Block Address Update Data NO Bad Block table = FFh? YES ...
Page 32
... After several updates it is necessary to remove invalid pages to free some memory space. To free this memory space and allow further program operations it is recommended to implement a garbage collection algorithm garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see Figure 17) ...
Page 33
... NAND512-A2C An ECC model is available in VHDL or Verilog. Contact the nearest Numonyx sales office for more details. Figure 18. Error detection 7.6 Hardware simulation models 7.6.1 Behavioral simulation models Denali software corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior and timings of NAND flash devices, and so allow software to be developed before hardware ...
Page 34
Program and erase times and endurance cycles 8 Program and erase times and endurance cycles The program and erase times and the number of program/erase cycles per block are shown in Table 14. Table 14. Program, erase times and program ...
Page 35
NAND512-A2C 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under ...
Page 36
DC and AC parameters M Table 18. DC characteristics, 1.8 V devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input high ...
Page 37
NAND512-A2C Table 19. DC characteristics devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (TTL), DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input ...
Page 38
DC and AC parameters Table 21. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t ...
Page 39
NAND512-A2C Figure 20. Command Latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 21. Address Latch AC waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH (AL ...
Page 40
DC and AC parameters Figure 22. Data Input Latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O Figure 23. Sequential data output after read AC waveforms Low Low, W ...
Page 41
NAND512-A2C Figure 24. Read status register AC waveforms tCLHWH tELWH Figure 25. Read electronic signature AC waveforms I/O 90h Read Electronic Signature Command 1. Refer to Table 12 for the values of the manufacturer and ...
Page 42
DC and AC parameters Figure 26. Page read A/read B operation AC waveforms CL E tWLWL 00h or Add.N I/O 01h cycle 1 Command Code 42/55 tWHBL tALLRL2 tWHBH tRLRH tBLBH1 Data Add.N Add.N Add.N cycle ...
Page 43
... Figure 27. Read C operation, one page AC waveforms Add. M I/O 50h cycle 1 RB Command Code 1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are don’t care. tWHALL Add. M Add. M Add. M cycle 2 cycle 3 cycle 4 Address M Input Busy DC and AC parameters tWHBH tALLRL2 ...
Page 44
DC and AC parameters Figure 28. Page program AC waveforms CL E tWLWL (Write Cycle time Add.N I/O 80h cycle 1 RB Page Program Setup Code 44/55 tWLWL tWHBL Add.N Add.N Add.N N cycle 4 cycle 2 ...
Page 45
NAND512-A2C Figure 29. Block erase AC waveforms CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 30. Reset AC waveforms I/O FFh ...
Page 46
DC and AC parameters Figure 31. Program/erase enable waveforms W tVHWH WP RB I/O Figure 32. Program/erase disable waveforms W tVLWH WP High RB I/O 10.1 Ready/Busy signal electrical characteristics Figure 33, Figure 34 signal. The value required for the ...
Page 47
NAND512-A2C Figure 33. Ready/Busy AC waveform Figure 34. Ready/Busy load circuit 1.8 V device - 0 0.1 V 3.3 V device - 0 ...
Page 48
... DC and AC parameters Figure 35. Resistor value versus waveform timings for Ready/Busy signal 25°C. 10.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD Low ( guarantee hardware protection during power transitions as shown in the figure ...
Page 49
... NAND512-A2C 11 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
Page 50
Package mechanical Figure 38. VFBGA55 1. active ball array, 0.8 mm pitch, package outline FE1 FD1 Drawing is not to scale. 50/ ...
Page 51
NAND512-A2C Table 23. VFBGA55 1. active ball array, 0.8 mm pitch, mechanical data Symbol Typ 0.65 b 0.45 D 8.00 D1 4.00 D2 5.60 ddd E 10.00 ...
Page 52
Package mechanical Figure 39. VFBGA63 1. +15, 0.8 mm pitch, package outline FD1 BALL "A1" 1. Drawing is not to scale. Table 24. VFBGA63 ...
Page 53
... Option E = RoHS compliant package, standard packing F = RoHS compliant package, tape & reel packing Note: Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. NAND512R3A 2 C Ordering information ...
Page 54
... Table 19: DC characteristics devices LKO Read status register AC Minor text changes. 3 Applied Numonyx branding. Added the sequential row read option and the package VFBGA55 4 throughout the document. Document status upgraded from ‘full datasheet’ to ‘not for new design’. Added security features on the cover page and in Description ...
Page 55
... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...