NAND512W3A2CN6E NUMONYX, NAND512W3A2CN6E Datasheet - Page 30

IC FLASH 512MBIT 48TSOP

NAND512W3A2CN6E

Manufacturer Part Number
NAND512W3A2CN6E
Description
IC FLASH 512MBIT 48TSOP
Manufacturer
NUMONYX
Datasheet

Specifications of NAND512W3A2CN6E

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
512M (64M x 8)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Cell Type
NAND
Density
512Mb
Access Time (max)
12us
Interface Type
Parallel
Boot Type
Not Required
Address Bus
26b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
64M
Supply Current
20mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Compliant

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Software algorithms
7
7.1
7.2
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Software algorithms
This section gives information on the software algorithms that Numonyx recommends to
implement to manage the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are programmed and erased by Fowler-Nordheim tunneling using a
high voltage. Exposing the device to a high voltage for extended periods can cause the
oxide layer to be damaged. For this reason, the number of program and erase cycles is
limited (see
and it is recommended to implement garbage collection, a wear-leveling algorithm and an
error correction code, to extend the number of program and erase cycles and increase the
data retention.
To help integrate a NAND memory into an application Numonyx can provide a full range of
software solutions: file system, sector management, drivers, and code management.
Contact the nearest Numonyx sales office or visit www.numonyx.com for more details.
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices where all the blocks are valid. A bad block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block where the 6th byte (x8 device)/1st
word (x16 device) in the spare area of the 1st page does not contain FFh is a bad block.
The bad block information must be read before any erase is attempted as the bad block
information may be erased. For the system to be able to recognize the bad blocks based on
the original information it is recommended to create a bad block table following the flowchart
shown in
NAND flash memory failure modes
Over the lifetime of the device additional bad blocks may develop.
To implement a highly reliable system, all the possible failure modes must be considered:
Refer to
Program/erase failure: in this case the block has to be replaced by copying the data to a
valid block. These additional bad blocks can be identified as attempts to program or
erase them will give errors in the status register.
As the failure of a page program operation does not affect the data in other pages in the
same block, the block can be replaced by re-programming the current data and copying
the rest of the replaced block to an available valid block. The Copy Back Program
command can be used to copy the data to a valid block. See
program
Read failure: in this case, ECC correction must be implemented. To efficiently use the
memory space, it is mandatory to recover single-bit errors, which occur during read
operations, by using ECC without replacing the whole block.
Table 13
Figure
Table 14: Program, erase times and program erase endurance cycles
for more details
16.
for the procedure to follow if an error occurs during an operation.
Section 6.4: Copy back
NAND512-A2C
for value)

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