XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 5

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Pinout and Signal Descriptions
See
Table 2: Signal Names
Address Inputs (A22-A0)
The Address inputs select the words in the memory array to
access during Bus Read operations. During Bus Write
operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ15-DQ0)
The Data I/O output the data stored at the selected address
during a Bus Read operation or input a command or the
data to be programmed during a Bus Write operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic,
input buffers, decoders and sense amplifiers. When Chip
Enable is at V
mode. When Chip Enable is at V
DS617 (v3.0.1) January 07, 2010
Product Specification
Notes:
1.
READY_WAIT
Signal Name
Typically, V
Program Supply Voltage section for alternate options.
Figure 5
DQ15-DQ0
A22-A0
V
V
V
V
V
WP
NC
RP
DDQ
SSQ
W
G
E
K
L
DD
PP
SS
R
and
PP
IL
and Reset is at V
is tied to the V
Table 2
Input/Output Buffers
Ground Input/output
Data Input/Outputs,
Program and Erase
Supply Voltage for
Optional
Command Inputs
Voltage for Fast
Address Inputs
Supply Voltage
Not Connected
Output Enable
Latch Enable
Write Enable
Write Protect
Chip Enable
Ready/Wait
Function
Internally
for a logic diagram and brief overview of the signals connected to this device.
Ground
Supply
Reset
Clock
DDQ
(1)
Supply
supply on a board. See the V
IH
IH
, the memory is
, the device is in active
Direction
Inputs
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
–
–
–
–
–
–
Platform Flash XL High-Density Configuration and Storage Device
www.xilinx.com
PP
X-Ref Target - Figure 5
deselected, the outputs are high impedance, and the power
consumption is reduced to the standby level.
Output Enable (G)
The Output Enable input controls data outputs during the
Bus Read operation of the memory. Before the start of the
first address latching sequence (FALS), the Output Enable
input must be held Low before the clock starts toggling.
Write Enable (W)
The Write Enable input controls the Bus Write operation of
the memory’s Command Interface. The data and address
inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
A22–A0
WP
RP
W
G
E
L
K
23
Figure 5: Logic Diagram
V
DD
V
SS
Flash XL
Platform
V
DDQ
V
SSQ
V
PP
16
DQ15–DQ0
READY_WAIT
DS617_05_053008
5