XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 68

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Table 45: Bank and Erase Block Region 2 Information
DS617 (v3.0.1) January 07, 2010
Product Specification
Notes:
1.
2.
The variable P is a pointer which is defined at CFI offset 015h.
Bank Regions. There are two Bank Regions, see
(P+3A)h = 144h
(P+3B)h = 145h
(P+3C)h = 146h
(P+3D)h = 147h
(P+3E)h = 148h
(P+3F)h = 149h
(P+32)h = 13Ch
(P+33)h = 13Dh
(P+34)h = 13Eh
(P+35)h = 13Fh
(P+36)h = 140h
(P+37)h = 141h
(P+38)h = 142h
(P+39)h = 143h
(P+40)h = 14Ah
(P+41)h = 14Bh
(P+42)h = 14Ch
(P+43)h = 14Dh
(P+44)h = 14Eh
(P+45)h = 14Fh
(P+46)h = 150h
(P+47)h = 151h
(P+48)h = 152h
(P+49)h = 153h
Offset
R
Data
01h
00h
11h
00h
00h
02h
06h
00h
00h
02h
64h
00h
01h
03h
03h
00h
80h
00h
64h
00h
01h
03h
–
–
Number of identical banks within Bank Region 2
Number of program or erase operations allowed in Bank Region 2:
Number of program or erase operations allowed in other banks while a bank in this region is
programming
Number of program or erase operations allowed in other banks while a bank in this region is
erasing
Types of erase block regions in Bank Region 2 n = number of erase block regions with
contiguous same-sized erase blocks. Symmetrically blocked banks have one blocking
region.
Bank Region 2 Erase Block Type 1 Information
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 1): Bits per cell, internal ECC
Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined
in
Bank Region 2 Erase Block Type 2 Information
Bank Region 2 (Erase Block Type 2)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 2): Bits per cell, internal ECC
Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined
in
Feature Space definitions
Reserved
Table 42, page 68
Table 42, page 68
Bits 0–3: Number of simultaneous program operations
Bits 4–7: Number of simultaneous erase operations
Bits 0–3: Number of simultaneous program operations
Bits 4–7: Number of simultaneous erase operations
Bits 0–3: Number of simultaneous program operations
Bits 4–7: Number of simultaneous erase operations
Bits 0–15: n+1 = number of identical-sized erase blocks
Bits 16–31: n×256 = number of bytes in erase block region
Bits 0–3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5–7: reserved
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3–7: reserved
Bits 0–15: n+1 = number of identical-sized erase blocks
Bits 16–31: n×256 = number of bytes in erase block region
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5–7: reserved
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3–7: reserved
(2)
Table 35, page
Platform Flash XL High-Density Configuration and Storage Device
www.xilinx.com
)
)
(1,2)
61.
Description
68