PCA85162T/Q900/1,1 NXP Semiconductors, PCA85162T/Q900/1,1 Datasheet - Page 21
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PCA85162T/Q900/1,1
Manufacturer Part Number
PCA85162T/Q900/1,1
Description
IC INTERFACE
Manufacturer
NXP Semiconductors
Datasheet
1.PCA85162TQ90011.pdf
(42 pages)
Specifications of PCA85162T/Q900/1,1
Package / Case
48-TSSOP
Display Type
LCD
Configuration
32 Segment
Interface
I²C
Current - Supply
80µA
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 95°C
Mounting Type
Surface Mount
Number Of Digits
16
Number Of Segments
32
Maximum Clock Frequency
4800 Hz
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 95 C
Attached Touch Screen
No
Maximum Supply Current
20 uA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Digits Or Characters
-
Lead Free Status / Rohs Status
Details
Other names
568-5119-2
NXP Semiconductors
PCA85162_1
Product data sheet
The I
condition (S) from the I
slave addresses available. All PCA85162 whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I
ignored by all PCA85162 whose SA0 inputs are set to the alternative level.
After an acknowledgement, one or more command bytes follow that define the status of
each addressed PCA85162.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C (see
PCA85162 on the bus.
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data directed to the intended PCA85162 device.
An acknowledgement after each byte is asserted only by the PCA85162 that are
addressed via address lines A0, A1, and A2. After the last display byte, the I
master asserts a STOP condition (P). Alternately a START may be asserted to restart an
I
2
Fig 15. I
Fig 16. Format of command byte
•
•
C-bus access.
Up to 16 PCA85162 for very large LCD applications
The use of two types of LCD multiplex drive
2
C-bus protocol is shown in
2
S
Figure
C-bus protocol
0 1 1 1 0 0
slave address
All information provided in this document is subject to legal disclaimers.
16). The command bytes are also acknowledged by all addressed
1 byte
2
Rev. 01 — 19 April 2010
C-bus master which is followed by one of two possible PCA85162
S
A
0
R/W
MSB
0 A C
C
Figure
acknowledge by
all addressed
n ≥ 1 byte(s)
PCA85162
COMMAND
REST OF OPCODE
15. The sequence is initiated with a START
Universal LCD driver for low multiplex rates
A
msa833
DISPLAY DATA
n ≥ 0 byte(s)
LSB
by A0, A1 and A2
update data pointers
subaddress counter
PCA85162 only
PCA85162
and if necessary,
acknowledge
selected
2
C-bus transfer is
© NXP B.V. 2010. All rights reserved.
A
013aaa057
P
2
C-bus
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