PCA9512AD,112 NXP Semiconductors, PCA9512AD,112 Datasheet - Page 7

• Manufacturer Part Number: PCA9512AD,112
• Description: IC LEVSHIFT I2C/SMBUS BUFF 8SOIC
• Manufacturer: NXP Semiconductors
• Type: I²C-Bus and SMBus Switchr

Specifications of PCA9512AD,112

• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Applications: Hot-Swap/SMB Buffer
• Internal Switch(s): Yes
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: PCA
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 3 / 3
• Logic Type: Bus Buffer
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3361-5; 935279721112; PCA9512AD

NXP Semiconductors
PCA9512A_PCA9512B
Product data sheet
8.5 Rise time accelerators
8.6 ACC boost current enable
8.7 Resistor pull-up value selection
slew rate is slow enough that the output catches up it will still lag the falling voltage of the
input by the offset voltage. The maximum t
zero delay and the output is still limited by its turn-on delay and the falling edge slew rate.
The output falling edge slew rate is a function of the internal maximum slew rate which is
a function of temperature, V
load capacitance.
During positive bus transactions, a 2 mA current source is switched on to quickly slew the
SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9512A/B is exceeded.
The rising edge rate should be at least 1.25 V/μs to guarantee turn on of the accelerators.
The built-in ΔV/Δt rise time accelerators on all SDA and SCL lines requires the bus pull-up
voltage and respective supply voltage (V
rise time accelerators can be disabled through the ACC pin for lightly loaded systems.
Users having lightly loaded systems may wish to disable the rise time accelerators.
Driving this pin to ground turns off the rise time accelerators on all four SDAn and SCLn
pins. Driving this pin to the V
accelerators.
The system pull-up resistors must be strong enough to provide a positive slew rate of
1.25 V/μs on the SDAn and SCLn pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value using the formula given in
Equation
where R
and C is the equivalent bus capacitance in picofarads.
In addition, regardless of the bus capacitance, always choose R
V
requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the
card, and these pull-up values are needed to overcome the precharge voltage. See the
curves in
R
CC
PU
= 5.5 V maximum, R
≤
800
PU
1:
Figure 5
×
is the pull-up resistor value in Ω, V
10
3
All information provided in this document is subject to legal disclaimers.
⎛
⎝
V
---------------------------------- -
CC min
and
(
C
Rev. 5 — 5 January 2011
Figure 6
)
PU
Level shifting hot swappable I
–
0.6
CC
≤ 45 kΩ for V
CC2
⎞
⎠
or V
for guidance in resistor pull-up selection.
voltage enables normal operation of the rise time
CC2
and process, as well as the load current and the
CC
PCA9512A; PCA9512B
CC
PHL
or V
= 3.6 V maximum. The start-up circuitry
CC(min)
occurs when the input is driven LOW with
CC2
) to be the same. The built-in ΔV/Δt
is the minimum V
2
C-bus and SMBus bus buffer
PU
≤ 65.7 kΩ for
CC
© NXP B.V. 2011. All rights reserved.
voltage in volts,
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