ADT7317ARQ-REEL Analog Devices Inc, ADT7317ARQ-REEL Datasheet - Page 11

• Manufacturer Part Number: ADT7317ARQ-REEL
• Description: IC SENSOR TEMP 10BIT DAC 16QSOP
• Manufacturer: Analog Devices Inc

Specifications of ADT7317ARQ-REEL

• Rohs Status: RoHS non-compliant
• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 120°C, External Sensor
• Output Type: I²C™, MICROWIRE™, QSPI™, SMBus™, SPI™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 120°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
V
V
V
CS
GND
V
D+
D−
LDAC
INT/INT
DOUT/ADD
SDA/DIN
SCL/SCLK
V
V
V
OUT
OUT
REF
DD
REF
OUT
OUT
-AB
-CD
-B
-A
-D
-C
Description
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Reference Input Pin for DAC A and DAC B. It may be configured as a buffered or unbuffered input to both DAC A
SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it
Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
Positive connection to external temperature sensor.
Negative connection to external temperature sensor.
Active low control input that transfers the contents of the input registers to their respective DAC registers. A falling
Over-Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
DOUT: SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on
ADD: I
SDA: I
DIN: SPI Serial Data Input. Serial data to be loaded into the device registers is provided on this input. Data is
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register
Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to both DAC C
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
and DAC B. It has an input range from 0.25 V to V
DAC A and DAC B default on power-up to this pin.
enables the input register, and data is transferred in on the rising edges and out on the falling edges of the
subsequent serial clocks. It is recommended that this pin be tied high to V
in I
edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum
pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows
simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin.
Default is with the LDAC pin controlling the loading of DAC registers.
temperature or V
the falling edge of SCLK. Open-drain output—needs a pull-up resistor.
floating gives the address 1001 010, and setting it high gives the address 1001 011. The I
ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the
second valid communication, the serial bus address is latched in. Any subsequent changes on this pin have no
affect on the I
drain configuration—needs a pull-up resistor.
clocked into a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor.
of the ADT7316/ADT7317/ADT7318 and also to clock data into any register that can be written to. Open-drain
configuration; needs a pull-up resistor.
and DAC D. It has an input range from 0.25 V to V
DAC C and DAC D default, on power-up, to this pin.
2
C mode.
2
2
C Serial Data Input. I
C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000, leaving it
2
C serial bus address.
DD
limits are exceeded. Default is active low. Open-drain output—needs a pull-up resistor.
V
2
V
V
REF
C serial data that is loaded into the device registers is provided on this input. Open-
OUT
OUT
GND
V
-AB
Figure 9. Pin Configuration QSOP
CS
D+
DD
D–
-B
-A
1
2
3
4
5
6
7
8
Rev. B | Page 11 of 44
(Not to Scale)
ADT7316/
ADT7317/
ADT7318
TOP VIEW
DD
DD
16
15
14
13
12
11
10
9
in unbuffered mode and from 1 V to V
in unbuffered mode and from 1 V to V
V
V
V
SCL/SCLK
SDA/DIN
DOUT/ADD
INT/INT
LDAC
OUT
OUT
REF
-CD
-C
-D
ADT7316/ADT7317/ADT7318
DD
when operating the serial interface
2
DD
C address set up by the
DD
in buffered mode.
in buffered mode.