ADT7317ARQ-REEL Analog Devices Inc, ADT7317ARQ-REEL Datasheet - Page 36

• Manufacturer Part Number: ADT7317ARQ-REEL
• Description: IC SENSOR TEMP 10BIT DAC 16QSOP
• Manufacturer: Analog Devices Inc

Specifications of ADT7317ARQ-REEL

• Rohs Status: RoHS non-compliant
• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 120°C, External Sensor
• Output Type: I²C™, MICROWIRE™, QSPI™, SMBus™, SPI™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 120°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP

ADT7316/ADT7317/ADT7318
SERIAL INTERFACE
There are two serial interfaces that can be used on this part, the
I
interface in I
stay in I
line to either V
mode, but it is possible to select and lock the SPI mode.
To select and lock the interface into the SPI mode, a number
of pulses must be sent down the CS (Pin 4) line. The following
section describes how this is done.
Once the SPI communication protocol has been locked in, it
cannot be unlocked while the device is still powered up. Bit D0
of the SPI Lock Status register (Address 0x7F) is set to 1 when a
successful SPI interface lock has been accomplished. To reset
the serial interface, the user must power down the part and power
up again. A software reset does not reset the serial interface.
SERIAL INTERFACE SELECTION
The CS line controls the selection between I
Figure 50 shows the selection process necessary to lock the
SPI interface mode.
To communicate to the ADT7316/ADT7317/ADT7318 using
the SPI protocol, send three pulses down the CS line, as shown
in Figure 50. On the third rising edge (marked as C in Figure 50),
the part selects and locks the SPI interface. The user is limited
to communicating to the device using the SPI protocol.
As per most SPI standards, the CS line must be low during every
SPI communication to the ADT7316/ADT7317/ ADT7318 and
high all other times. Typical examples of how to connect the
dual interface as I
The following sections describe in detail how to use the I
and SPI protocols associated with the ADT7316/ADT7317/
ADT7318.
I
Like all I
ADT7318 have a 7-bit serial address. The 4 MSBs of this
address for the ADT7316/ADT7317/ADT7318 are set to
1001. The 3 LSBs are set by Pin 11, ADD. The ADD pin
can be configured three ways to give three different address
options: low, floating, and high. Setting the ADD pin low
gives a serial bus address of 1001 000, leaving it floating gives
the address 1001 010, and setting it high gives the address
1001 011. The recommended pull-up resistor value is 10 kΩ.
There is a programmable SMBus timeout. When this is enabled
the SMBus times out after 25 ms of no activity. To enable it, set
Bit 6 of the Control Configuration 2 register (Address 0x19). The
power-up default is with the SMBus timeout disabled.
The ADT7316/ADT7317/ADT7318 support SMBus packet
error checking (PEC) and its use is optional. It is triggered by
supplying the extra clocks for the PEC byte. The PEC byte is
2
2
C and the SPI interface. The device powers up with the serial
C SERIAL INTERFACE
2
C mode, it is recommended that the user ties the CS
2
C-compatible devices, the ADT7316/ADT7317/
2
C mode, but it is not locked into this mode. To
CC
2
C or SPI are shown in Figure 48 and Figure 49.
or GND. It is not possible to lock the I
2
C and SPI.
2
C
2
C
Rev. B | Page 36 of 44
calculated using CRC-8. The frame clock sequence (FCS)
conforms to CRC-8 by the polynomial:
Consult SMBus for more information.
The serial bus protocol operates as follows:
1.
2.
3.
Any number of bytes of data may be transferred over the serial
bus in one operation. However, reads and writes cannot be mixed
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
The I
until after this address has been sent twice. On the eighth SCL
cycle of the second valid communication, the serial bus address
is latched in. This is the SCL cycle directly after the device has
seen its own I
this pin have no effect on the I
C(x) = x
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, consisting of a 7-bit
address (MSB first) plus an R/ W bit, which determines the
direction of the data transfer, that is, whether data is to be
written to or read from the slave device. The peripheral
whose address corresponds to the transmitted address
responds by pulling the data line low during the low period
before the ninth clock pulse, known as the acknowledge
bit. All other devices on the bus now remain idle, while the
selected device waits for data to be read from or written to
it. If the R/ W bit is 0, the master writes to the slave device.
If the R/ W bit is 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses, 8 bits of data followed by an acknowledge bit from
the receiver of data. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, because a low-to-high transition
when the clock is high may be interpreted as a stop signal.
When all data bytes have been read or written, stop condi-
tions are established. In write mode, the master pulls the
data line high during the 10th clock pulse to assert a stop
condition. In read mode, the master device pulls the data
line high during the low period before the ninth clock
pulse. This is known as no acknowledge. The master takes
the data line low during the low period before the 10th
clock pulse, then high during the 10th clock pulse to assert
a stop condition.
2
C address set up by the ADD pin is not latched by the device
8
2
+ x
C serial bus address. Any subsequent changes on
2
+ x
1
+ 1
2
C serial bus address.