IDT72V51253L6BB8 IDT, Integrated Device Technology Inc, IDT72V51253L6BB8 Datasheet

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IDT72V51253L6BB8

Manufacturer Part Number
IDT72V51253L6BB8
Description
IC FLOW CTRL MULTI QUEUE 256-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT72V51253L6BB8

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V51253L6BB8

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Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V51253L6BB8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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FEATURES:
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FUNCTIONAL BLOCK DIAGRAM
Choose from among the following memory density options:
IDT72V51233
IDT72V51243
IDT72V51253
Configurable from 1 to 4 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
Independent Read and Write access per queue
User programmable via serial port
Default multi-queue device configurations
-IDT72V51233: 8,192 x 18 x 4Q or 16,384 x 9 x 4Q
-IDT72V51243: 16,384 x 18 x 4Q or 32,768 x 9 x 4Q
-IDT72V51253: 32,768 x 18 x 4Q or 65,536 x 9 x 4Q
100% Bus Utilization, Read and Write on every clock cycle
166 MHz High speed operation (6ns cycle time)
3.7ns access time
WRADD
WADEN
WCLK
FSTR
PAFn
WEN
PAF
FF
DATA IN
x9, x18
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯
5
D in
4
Total Available Memory = 589,824 bits
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
MULTI-QUEUE FLOW-CONTROL DEVICE
3.3V MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION
589,824 bits
1,179,648 bits
2,359,296 bits
Q
Q
0
3
1
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Individual, Active queue flags (OV, FF, PAE, PAF)
4 bit parallel flag status on both read and write ports
Provides continuous PAE and PAF status of up to 4 Queues
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
- x18in to x18out
- x9in to x18out
- x18in to x9out
- x9in to x9out
FWFT mode of operation on read port
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
5941 drw01
FEBRUARY 2009
Q out
4
6
x9, x18
DATA OUT
IDT72V51233
IDT72V51243
IDT72V51253
OV
PAE
PAEn
RADEN
ESTR
RDADD
REN
RCLK
OE
DSC-5941/10

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IDT72V51253L6BB8 Summary of contents

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MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824 bits 1,179,648 bits 2,359,296 bits FEATURES: • • • • • Choose from among the following memory density options: ⎯ ⎯ ⎯ ⎯ ⎯ IDT72V51233 Total Available Memory = ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits DESCRIPTION: The IDT72V51233/72V51243/72V51253 multi-queue flow-control de- vices are single chip within which anywhere between 1 and 4 discrete FIFO queues can be setup. All ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK WEN 5 WRADD Write Control WADEN Logic Write Pointers PAF FSTR 4 General Flag PAFn Monitor FSYNC FXO FXI Active Q FF Flags ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN CONFIGURATION A1 BALL PAD CORNER A D14 D13 D12 D10 B D15 D16 D11 D9 C D17 GND GND D8 D GND GND ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits DETAILED DESCRIPTION MULTI-QUEUE STRUCTURE The IDT multi-queue flow-control device has a single data input port and single data output port with ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS Symbol & Name I/O TYPE Pin No. D[17:0] Data Input Bus LVTTL Din (See Pin INPUT table for details) (1) DF Default ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. PAFn Bus Sync FSYNC LVTTL OUTPUT during Polled operation of the PAFn bus. During ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. PAE Programmable LVTTL (P10) Almost-Empty Flag OUTPUT for read operations, (selected via RCLK, RDADD ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. RDADD Read Address Bus LVTTL [5:0] INPUT (Continued) (RDADD5-P16 RDADD4-P15 RDADD3-P14 RDADD2-N14 RDADD1-M16 RDADD0-M15) ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. (2) TDO JTAG Test Data LVTTL (A9) Output OUTPUT operation, test data serially loaded ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PIN NUMBER TABLE Symbol Name I/O TYPE D[17:0] Data Input Bus LVTTL Din INPUT Q[17:0] Data Output Bus LVTTL Qout OUTPUT Q7-C13, Q6-A12, Q5-B12, ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTE: 1. ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits AC TEST LOADS Ω I/O Figure 2a. AC Test Load AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits AC ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.15V 0°C to +70°C;Industrial Symbol Parameter f Clock Cycle Frequency (WCLK ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits AC ELECTRICAL CHARACTERISTICS (CONTINUED) (Commercial 3.3V ± 0.15V 0°C to +70°C;Industrial Symbol Parameter RCLK to PAE Flag ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits FUNCTIONAL DESCRIPTION MASTER RESET A Master Reset is performed by toggling the MRS input from HIGH to LOW to HIGH. During a master reset ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits When configuring the IDT72V51233/72V51243/72V51253 devices in de- fault mode the user simply has to apply WCLK cycles after a master reset, until SENO goes ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits READ QUEUE SELECTION & READ OPERATION The multi-queue flow-control device has queues that data is read from via a common read ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits NULL QUEUE OPERATION (OF THE READ PORT) Pipelining of data to the output port enables the device to provide 100% bus utilization in standard ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits OUTPUT VALID FLAG OPERATION The multi-queue flow-control device provides a single Output Valid flag output, OV. The OV provides an empty status or data ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits within a queue can be at any point within that queues depth. This location can be user programmed via the serial port or one ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING Output Valid, OV Flag Boundary I/O Set-Up OV Goes LOW after 1 In18 to out18 or ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED) Programmable Almost Empty Flag, PAE Boundary I/O Set-Up In18 to out18 or In9 to out9 ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits PAFn FLAG BUS OPERATION The IDT72V51233/72V51243/72V51253 multi-queue flow-control devices can be configured for queues, each queue having its own almost full ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits the devices connected in expansion. In expansion mode one device will be set as the Master, MAST input tied HIGH, all other devices will ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits MRS t RSS WEN REN t RSS SENI t RSS FSTR, ESTR t RSS WADEN, RADEN t RSS ID0, ID1, ID2 t RSS OW, ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits w-2 WCLK WADEN WEN t AS WRADD Qx FF PAF Active Bus PAF-Qx (5) PRS RCLK REN t QS RADEN t ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 29 TEMPERATURE RANGES ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 30 TEMPERATURE RANGES ...

Page 31

IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 31 TEMPERATURE RANGES ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK t ENS WEN RCLK REN Qout Last Word Read Out of Queue OV NOTES has ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 33 TEMPERATURE RANGES ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 34 TEMPERATURE RANGES ...

Page 35

IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK t ENS REN RDADD Addr=001011 RADEN Qout (Device 1) ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK t t ENS ENH REN t AS RDADD t QS RADEN OUT ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits NULL QUEUE RCLK t AS RDADD t QS RADEN REN t A Qout Q1 Wn-3 Q1 Wn-2 OV NOTES: 1. The purpose of the ...

Page 38

IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* WCLK WEN WRADD WADEN Din PAF HIGH-Z (Device 1) PAF (Device ...

Page 39

IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* *B* RCLK REN HIGH RDADD RADEN HIGH-Z Qout PAE HIGH-Z (Device ...

Page 40

IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* WCLK WADEN FSTR t ENS WEN WRADD D5Q3 100 Writes to Previous ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits *A* RCLK RADEN ESTR REN RDADD D0Q1 000 001 OE t OLZ Qout W Prev. Q ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits WCLK FSYNC 0 (MASTER) FXO 0 / FXI 1 FSYNC 1 (SLAVE) FXO 1 / FXI 2 FSYNC 2 (SLAVE) FXO 2 / FXI ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits RCLK ESYNC 0 EXO 0 / EXI 1 ESYNC 1 EXO 1 / FXI 2 ESYNC 2 EXO 2 / EXI 0 PAE n ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits Serial Programming Data Input Serial Enable Data Bus Write Clock Write Enable Write Queue Select Write Address Full Strobe Programmable Almost Full Full Sync1 ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V51233/72V51243/ 72V51253 incorporates ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits 1 0 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and ...

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IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits t 1 TCK t 3 TDI/ TMS t TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t ...

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ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order. DATASHEET DOCUMENT HISTORY 10/10/2001 pgs ...

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