IDT77V500S25BCG IDT, Integrated Device Technology Inc, IDT77V500S25BCG Datasheet - Page 12

• Manufacturer Part Number: IDT77V500S25BCG
• Description: IC SW MEMORY 8X8 1.2BGPS 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V500S25BCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 77V500S25BCG

CBR Clock Functional Waveform Example 1 - CBR Frame Implementation
CBR Clock Functional Waveform Example 1 - CBR Frame Implementation
CBR Clock Functional Waveform Example 1 - CBR Frame Implementation
CBR Clock Functional Waveform Example 1 - CBR Frame Implementation
(Fast CBRCLK with Frame Timing)
(Fast CBRCLK with Frame Timing)
(Fast CBRCLK with Frame Timing)
(Fast CBRCLK with Frame Timing)
which CBRCLK is used (CBRCLK2 or CBRCLK3) ("y" represents the specific output (0-7)). The OPyCBRx VC List for this example is defined in Figure
3.
CBR Clock Functional Waveform Example 2 - VBR/CBR Implementation
CBR Clock Functional Waveform Example 2 - VBR/CBR Implementation
CBR Clock Functional Waveform Example 2 - VBR/CBR Implementation
CBR Clock Functional Waveform Example 2 - VBR/CBR Implementation
(t (t (t (t
or 3, depending on which CBRCLK is used (CBRCLK2 or CBRCLK3). ("y" represents the specific output (0-7)) The OPyCBRx VC List for this example
is defined in Figure 3.
Reset Waveforms
Reset Waveforms
Reset Waveforms
Reset Waveforms
CBRCLKx
CBRCLKx
1
2
3
1
2
3
1
plete.
2
IDT77V500
CBRCLKx must be HIGH for eight clocks or more to reinitiate the transmission sequence at the start of the OPyCBRx VC List.
A cell from a VC on the OPyCBRx VC List is scheduled on each rising clock edge of SCLK after a falling edge of CBRCLKx if the previous VC has completed internal processing.
This example shows four VCs in the OPyCBRx VC List. The number of VCs in the OPxCBRx VC List may be as large as 8192.
The period between reinitiation of the OPyCBRx VC List defines the frame size; that is, the amount of time between starting the transmissions from the top of the OPyCBRx VC List.
A cell from a VC on the OPyCBRx VC List is scheduled on each rising edge of SCLK after a falling edge of CBRCLKx.
tCHx > 8 SCLK so that a cell is scheduled after each falling edge of CBRCLKx.
The pointer has moved back to the beginning of the OPyCBRx VC List.
RESETI must be held HIGH for 8 SCLK cycles. When RESETI goes Low again 8191 cycles are used prior to the Status Acknowledge bits showing the internal reset process is com-
This delay should typically be much less than two SCLK cycles. RESETO remains High until START Command is received from the Call Setup Manager.
CH
CH
waveform
CH
CH
This example shows the procedure recommended for use of direct CBR scheduling. "x" for this waveform represents either 2 or 3, depending on
This example shows the use of a slower CBRCLK (tCHx > 8 SCLK) to provide VBR/CBR traffic shaping. For this waveform "x" represents either 2
SCLK
RESETO
RESETI
cont'd
SCLK
SCLK
x > 8 SCLK)
x > 8 SCLK)
x > 8 SCLK)
x > 8 SCLK)
1
100
2 clock cycles max.
1
100
1
200
2
2
t
RSI
400
1
300
7
2
2
400
8
12 of 17
200
3
1
2
100
1
100
3
8190
200
300
8191
2
300
400
April 11, 2001
1
3607 drw 14
see cont'd
waveform
3607 drw 12
3607 drw 13
2