IDT77V500S25BCG IDT, Integrated Device Technology Inc, IDT77V500S25BCG Datasheet - Page 8

• Manufacturer Part Number: IDT77V500S25BCG
• Description: IC SW MEMORY 8X8 1.2BGPS 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V500S25BCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 77V500S25BCG

AC Electrical Characteristics Over the Operating Temperature Range
AC Electrical Characteristics Over the Operating Temperature Range
AC Electrical Characteristics Over the Operating Temperature Range
AC Electrical Characteristics Over the Operating Temperature Range
(Vcc = 3.3V ± 0.3V)
(Vcc = 3.3V ± 0.3V)
(Vcc = 3.3V ± 0.3V)
(Vcc = 3.3V ± 0.3V)
IDT77V500
1.
indicate that the internal reset process in complete.
2.
device characterization, but is not production tested.
3.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC
CH
CL
R
F
MCYC
MCH
MCL
SM
HM
SMRW
HMRW
SMD
HMD
SCRC
HCRC
SIO
HIO
OFP
CDC
DCC
CDS
DCS
CDIO
DCIO
AMD
OHMD
CDOF
DCOF
RSI
RSO
CDR
CKHZ
CKLZ
CYC3
CH3
CL3
CYC2
CH2
CL2
RESETI must be held High for 8 SCLK cycles. After RESETI transitions Low, 8191 cycles are required before the Status Acknowledge bits will
Transition is measured +/-200mV from Low or High impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by
Cycle units insure that the SCLK recognizes the state of CBRCLK.
Symbol
System Clock Cycle Time
System Clock High Time
System Clock Low Time
Clock Rise Time
Clock Fall Time
Manager Clock Cycle Time
Manager Clock High Time
Manager Clock Low Time
MD/C Setup Time to MSTRB High
MD/C Hold Time after MSTRB High
MR/W Setup Time to MSTRB High
MR/W Hold Time after MSTRB High
MDATA Setup Time to MSTRB High
MDATA Hold Time after MSTRB High
CRCERR Setup Time to SCLK High
CRCERR Hold Time after SCLK High
IOD Setup Time to SCLK High
IOD Hold Time after SCLK High
OFRM High Pulse Width
SCLK to CMD Valid
CMD Output Hold after SCLK High
SCLK to SFRM Valid
SFRM Output Hold after SCLK High
SCLK to IOD Valid
IOD Output Hold after SCLK High
MSTRB Low to MDATA Valid
MDATA Output Hold after MSTRB High
SCLK to OFRM/CBUS Valid
OFRM/CBUS Output Hold after SCLK High
RESETI High Pulse Width
RESETO High after RESETI High
SCLK to RESETO Valid
SCLK High to Output High-Z
SCLK High to Output Low-Z
CBRCLK3 Clock Cycle Time
CBRCLK3 Clock High Time
CBRCLK3 Clock Low Time
CBRCLK2 Clock Cycle Time
CBRCLK2 Clock High Time
CBRCLK2 Clock Low Time
Parameter
1
3
3
3
3
2
2
3
3
8 of 17
Min.
25
10
10
—
—
25
6
19
10
2
10
2
10
2
5
2
5
2
5
—
2
—
2
—
2
—
2
—
2
8
—
—
—
2
3
1.2
1.2
3
1.2
1.2
77V500S25 Com’l & Ind
Max.
—
—
—
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18
—
18
—
18
—
18
—
18
—
—
2
18
10
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
ns
ns
ns
t
t
t
t
t
t
CYC
CYC
CYC
CYC
CYC
CYC
CYC
CYC
Unit
April 11, 2001