IDT77V500S25BCG IDT, Integrated Device Technology Inc, IDT77V500S25BCG Datasheet - Page 5

• Manufacturer Part Number: IDT77V500S25BCG
• Description: IC SW MEMORY 8X8 1.2BGPS 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V500S25BCG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 77V500S25BCG

TQFP Pin Description
TQFP Pin Description
TQFP Pin Description
TQFP Pin Description
18
22,20
86
2
3
4
17
19
7-9, 12-14
24
40-43, 46-49, 53-56, 59-66,
69-73, 77-79, 82-85
1, 90-93, 96-98
25, 28-29, 32-35, 36
11, 31, 45, 58, 68, 81, 87-
89, 94
10, 30, 37-39, 44, 57, 67,
80, 95
5-6, 15-16, 21, 23, 26-27,
50-52, 74-76, 99-100
IDT77V500
Pin Number
SCLK
CBRCLK3,
CBRCLK2
CRCERR
MD/C
MR/W
MSTRB
RESETI
RESETO
CMD0-5
SFRM
IOD0-31
MDATA0-7
OFRM1-7
OFRM0
VCC
VSS
NC
Symbol
I
I
I
I
I
I
I
O
O
O
I/O
I/O
I/O
Power
Power
____
Type
System clock: Reference clock input for all synchronous pins of the IDT77V500 Switch Controller. All synchro-
nous signals are referenced to the rising edge of SCLK.
CBR Clocks 3 and 2: External clock signals used when Constant Bit Rate (CBR) Service classes are utilized.
These clock signals correspond to Output Port priorities 3 and 2 respectively and are used to determine the
constant bit rate for the controller. Priority 3 is the highest priority. If CBR mode is not used these pins should
be pulled up to Vcc with a resistor with a recommended value of 5K ohm or less.
Cyclical Redundancy Check Error: Synchronous input on the rising edge of SCLK. CRCERR asserted LOW
by the IDT77V400 Switching Memory during a store operation indicates that a HEC CRC error has occurred in
the cell header.
Manager Control: Selects the data or control registers of the IDT77V500 for the Manager Bus Operation.
MD/C asserted HIGH selects the data registers, and MD/C LOW selects the command/status registers of the
IDT77V500.
Manager Read/Write: MR/W LOW will write the data on the Manager Bus into the registers selected by the
MD/C input. In write mode (MR/W LOW) the data on MDATA0-7 is written synchronously with respect to the
rising edge of MSTRB; in read mode (MR/W HIGH) the data is accessed asynchronously.
Manager Strobe: Input which acts as a clock for the Manager Bus (MDATA0-7). Other Manager Bus inputs are
synchronous to the rising edge of MSTRB during write operations (MR/W LOW) and must meet the specified
Setup and Hold parameters. MSTRB performs an asynchronous Output Enable function when a read opera-
tion (MR/W HIGH) is executed on the Manager Bus. When MSTRB is LOW and MR/W is HIGH (Read Mode)
the Manager Bus is enabled in output mode and the contents of the IDT77V500 registers (determined by the
MD/C input) are available to be read on MDATA0-7.
Reset Input: When asserted HIGH, this signal asynchronously initiates the internal reset sequence of the
IDT77V500.
Reset Output: Asserted HIGH upon initiating the reset of the IDT77V500 (RESETI HIGH). In multiple
IDT77V500 configurations, this output is connected to the RESETI input of the next controller in the chain.
RESETO will remain HIGH until a START command is received from the Call Setup Manager.
Command Bus: Synchronized with SCLK, instructions to be executed by the IDT77V400 Switching memory
are output by the IDT77V500 on this 6-bit bus.
Synchronize Output Frame: Synchronous output used when multiple IDT77V500's contend for a common bus.
The Master IDT77V500 generates this signal which then drives the OFRM0 input of the other IDT77V500s.
Control Data Bus: Synchronous with SCLK and one cycle latent to the Command Bus (CMD0-5). Used for
transfer of the header bytes, configuration register, error and status registers, and the cell memory address
between the IDT77V500 and the IDT77V400 Switching Memory.
Manager Bus: Communications between the Call Setup Manager and the IDT77V500 occur over this 8-bit bi-
directional bus. MD/C, MR/W, and MSTRB determine the mode and data type transferred across the MDATA
bus. Write operations are synchronous with respect to MSTRB, while MDATA behaves asynchronously for
read operations.
Output Frame: Asynchronous input pins used by the IDT77V500 to detect when the next cell can be loaded to
the specified IDT77V400 output port 0 through 7. When in multiple IDT77V500 configurations, the OFRM1-7
are redefined as CBUS1-7 for arbitration. OFRM0 is always an input pin (There is no CBUS0).
Power Supply (+3.3V ±300mV)
Ground
No Connect
5 of 17
Description
April 11, 2001