MT9VDDT3272HG-335G2 Micron Technology Inc, MT9VDDT3272HG-335G2 Datasheet - Page 8

• Manufacturer Part Number: MT9VDDT3272HG-335G2
• Description: MODULE DDR SDRAM 256MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT3272HG-335G2

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 167MHz
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 557-1135

General Description
Serial Presence-Detect Operation
PDF: 09005aef80804052/Source: 09005aef806e057b
DD9C16_32_64x72H.fm - Rev. E 1/08 EN
The MT9VDDT1672H, MT9VDDT3272H, and MT9VDDT6472H are high-speed, CMOS
dynamic random access, 128MB, 256MB, and 512MB memory modules organized in a
x72 configuration. These modules use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
DDR SDRAM modules incorporate serial presence-detect. The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes are programmed by Micron to identify the module type and various
SDRAM organizations and timing parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/WRITE operations between the master
(system logic) and the slave EEPROM device (DIMM) occur via a standard I
the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide
eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
module, permanently disabling hardware write protect.
128MB, 256MB, 512MB (x72, ECC, SR) 200-Pin DDR SDRAM SODIMM
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2004 Micron Technology, Inc. All rights reserved
SS
on the
2
C bus using