MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet - Page 24

• Manufacturer Part Number: MT8VDDT6432UY-5K1
• Description: MODULE DDR 256MB 100-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6432UY-5K1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 100-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
16.
17. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-
18. This is not a device limit. The device will operate with a negative value, but system
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
20. MIN (
21. The refresh period 64ms. This equates to an average refresh rate of 15.625µs (128MB)
22. The valid data window is derived by achieving other specifications:
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
25. To maintain a valid level, the transitioning edge of the input must:
26. JEDEC specifies CK and CK# input slew rate must be ≥ 1 V/ns (2 V/ns differentially).
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
28. V
29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
t
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (HZ) or begins driving (LZ).
driven signal should either be HIGH, LOW, or High-Z and that any signal transition
within the input switching region must follow valid input requirements. If DQS transi-
tions HIGH, above DC V
to
performance could be degraded due to bus turnaround.
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on
minimum absolute value for the respective parameter.
ments is the largest multiple of
or 7.8125µs (256MB, 512MB). However, an AUTO REFRESH command must be
asserted at least once every 140.6µs (128MB) or 70.3µs (256MB, 512MB); burst
refreshing or posting by the DRAM controller greater than eight refresh cycles is not
allowed.
t
tion to the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality
is uncertain. Figure 7, Derating Data Valid Window
curves for duty cycles ranging between 50/50 and 45/55.
during REFRESH command period (
standby).
the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be
added to
V/ns, functionality is uncertain. For -6, slew rates must be ≥ 0.5 V/ns.
the same amount.
HZ and
DQSQ, and
b. Reach at least the target AC level.
a. Sustain a constant slew rate from the current AC level through to the target AC
c. After the AC target level is reached, continue to maintain at least the target DC
DD
t
DQSH (MIN).
level, V
must not vary more than 4 percent if CKE is not active while any bank is active.
level, V
t
RC or
t
t
LZ transitions occur in the same access time windows as valid data transi-
DS and
IL
t
t
IL
RFC) for I
QH (
(AC) or V
(DC) or V
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
t
t
DH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4
QH =
IH
DD
IH
IH
t
(AC).
HP -
measurements is the smallest multiple of
(MIN) then it must not transition LOW, below DC V
(DC).
24
t
QHS). The data valid window derates in direct propor-
t
CK that meets the maximum absolute value for
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC [MIN]) else CKE is LOW (i.e., during
t
DQSS.
t
QH -
t
©2004, 2005 Micron Technology, Inc. All rights reserved.
RAS (MAX) for I
t
(DQSQ), shows derating
t
CK that meets the
DD
t
HP (
measure-
IH
Notes
t
CK/2),
, prior
t
RAS.